DSPIC30F5011 MICROCHIP [Microchip Technology], DSPIC30F5011 Datasheet - Page 132

• Manufacturer Part Number: DSPIC30F5011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F5011/5013
19.7
The analog input model of the 12-bit A/D converter is
shown in Figure 18-11. The total sampling time for the
A/D is a function of the internal amplifier settling time
and the holding capacitor charge time.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the voltage level on the analog input
pin. The source impedance (R
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D con-
verter, the maximum recommended source imped-
ance, R
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 19-2:
DS70116C-page 130
SS
) impedance combine to directly affect the time
S
A/D Acquisition Requirements
, is 2.5 k . After the analog input channel is
IC
), and the internal sampling switch
12-BIT A/D CONVERTER ANALOG INPUT MODEL
Note: C
Legend: C
VA
PIN
HOLD
Rs
S
HOLD
value depends on device package and is not tested. Effect of C
), the interconnect
) must be allowed
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
. The combined
C
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
Preliminary
V
DD
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
IC
500 nA
250
Sampling
Switch
R
 2004 Microchip Technology Inc.
SS
PIN
R
negligible if Rs
SS
V
SS
C
= DAC capacitance
= 18 pF
HOLD
3 k
2.5 k .