DSPIC30F5011 MICROCHIP [Microchip Technology], DSPIC30F5011 Datasheet - Page 16

• Manufacturer Part Number: DSPIC30F5011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F5011/5013
2.3
The dsPIC devices feature a 16/16-bit signed fractional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:
1.
2.
3.
4.
5.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DS70116C-page 14
DIVF
DIV.sd
DIV.sw or
DIV.s
DIV.ud
DIV.uw or
DIV.u
DIVF - 16/16 signed fractional divide
DIV.sd - 32/16 signed divide
DIV.ud - 32/16 unsigned divide
DIV.sw - 16/16 signed divide
DIV.uw - 16/16 unsigned divide
Instruction
Divide Support
DIVIDE INSTRUCTIONS
Signed fractional divide: Wm/Wn
Signed divide: (Wm+1:Wm)/Wn
Signed divide: Wm/Wn
Unsigned divide: (Wm+1:Wm)/Wn
Unsigned divide: Wm/Wn
W0; Rem
W0; Rem
Preliminary
W0; Rem
W0; Rem
W0; Rem
W1
W1
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion as shown in Table 2-1 (REPEAT will execute the tar-
get instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Function
Note:
W1
W1
W1
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
 2004 Microchip Technology Inc.