LPC1111 NXP [NXP Semiconductors], LPC1111 Datasheet
LPC1111
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LPC1111 Summary of contents
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... ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug. System tick timer. Memory (LPC1114 (LPC1113 (LPC1112 (LPC1111) on-chip flash programming memory. 8 kB SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. ...
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... HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 2 C-bus specification and Fast-mode Plus with a Lighting ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 2 UART I C/ SPI ADC RS-485 Fast+ channels ...
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... CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 (1) LQFP48 and PLCC44 packages only. Fig 1. LPC1111/12/13/14 block diagram LPC1111_12_13_14_1 Product data sheet SWD TEST/DEBUG INTERFACE ARM CORTEX-M0 FLASH 8/16/24/32 kB system bus slave slave AHB-LITE BUS ...
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... Pin configuration LQFP48 package LPC1111_12_13_14_1 Product data sheet LPC1113FBD48/301 LPC1114FBD48/301 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 36 PIO3_0/DTR 35 R/PIO1_2/AD3/CT32B1_MAT1 34 R/PIO1_1/AD2/CT32B1_MAT0 33 R/PIO1_0/AD1/CT32B1_CAP0 32 R/PIO0_11/AD0/CT32B0_MAT3 31 PIO2_11/SCK0 30 PIO1_10/AD6/CT16B1_MAT1 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 28 PIO0_9/MOSI0/CT16B0_MAT1 27 ...
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... Pin configuration PLCC44 package LPC1111_12_13_14_1 Product data sheet LPC1114FA44/301 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 39 R/PIO1_2/AD3/CT32B1_MAT1 38 R/PIO1_1/AD2/CT32B1_MAT0 37 R/PIO1_0/AD1/CT32B1_CAP0 36 R/PIO0_11/AD0/CT32B0_MAT3 35 PIO2_11/SCK0 34 PIO1_10/AD6/CT16B1_MAT1 33 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 32 PIO0_9/MOSI0/CT16B0_MAT1 31 PIO0_8/MISO0/CT16B0_MAT0 ...
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... XTALIN 5 XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 24 R/PIO1_2/AD3/CT32B1_MAT1 23 R/PIO1_1/AD2/CT32B1_MAT0 22 R/PIO1_0/AD1/CT32B1_CAP0 21 R/PIO0_11/AD0/CT32B0_MAT3 20 PIO1_10/AD6/CT16B1_MAT1 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 18 PIO0_9/MOSI0/CT16B0_MAT1 17 PIO0_8/MISO0/CT16B0_MAT0 002aae698 © NXP B.V. 2010. All rights reserved. ...
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... PIO0_11 — General purpose digital input/output pin. I AD0 — A/D converter, input 0. O CT32B0_MAT3 — Match output 3 for 32-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... PIO1_10 — General purpose digital input/output pin. I AD6 — A/D converter, input 6. O CT16B1_MAT1 — Match output 1 for 16-bit timer 1. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... PIO0_8 — General purpose digital input/output pin. I/O MISO0 — Master In Slave Out for SPI0. O CT16B0_MAT0 — Match output 0 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller …continued 2 C Fast-mode Plus. Figure Figure 26) ...
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... PIO1_6 — General purpose digital input/output pin. I RXD — Receiver input for UART. O CT32B0_MAT0 — Match output 0 for 32-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... PIO3_6 to PIO3_11 are not available. I/O PIO3_4 — General purpose digital input/output pin. I/O PIO3_5 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... Output from the oscillator amplifier. I Ground C-bus specification for I C standard mode and I All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 2 C Fast-mode Plus. Figure 26). © NXP B.V. 2010. All rights reserved. Figure 26). ...
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... NXP Semiconductors Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin PIO0_0 to PIO0_11 [1] RESET/PIO0_0 2 [2] PIO0_1/CLKOUT/ 3 CT32B0_MAT2 [2] PIO0_2/SSEL0/ 8 CT16B0_CAP0 [2] PIO0_3 9 [3] PIO0_4/SCL 10 [3] PIO0_5/SDA 11 [2] PIO0_6/SCK0 15 [2] PIO0_7/CTS 16 [2] PIO0_8/MISO0/ 17 CT16B0_MAT0 [2] PIO0_9/MOSI0/ 18 CT16B0_MAT1 [2] SWCLK/PIO0_10/SCK0/ 19 CT16B0_MAT2 [4] R/PIO0_11/AD0/ 21 CT32B0_MAT3 PIO1_0 to PIO1_11 LPC1111_12_13_14_1 Product data sheet ...
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... NXP Semiconductors Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin [4] R/PIO1_0/AD1/ 22 CT32B1_CAP0 [4] R/PIO1_1/AD2/ 23 CT32B1_MAT0 [4] R/PIO1_2/AD3/ 24 CT32B1_MAT1 [4] SWDIO/PIO1_3/AD4/ 25 CT32B1_MAT2 [4] PIO1_4/AD5/ 26 CT32B1_MAT3/WAKEUP [2] PIO1_5/RTS/ 30 CT32B0_CAP0 [2] PIO1_6/RXD/ 31 CT32B0_MAT0 [2] PIO1_7/TXD/ 32 CT32B0_MAT1 [2] PIO1_8/CT16B1_CAP0 7 [2] PIO1_9/CT16B1_MAT0 12 [4] PIO1_10/AD6/ 20 CT16B1_MAT1 [4] PIO1_11/AD7 27 LPC1111_12_13_14_1 Product data sheet Type Description I R — Reserved. Configure for an alternate function in the IOCONFIG block. ...
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... NXP Semiconductors Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin PIO2_0 [2] PIO2_0/DTR 1 PIO3_0 to PIO3_5 [2] PIO3_2 28 [2] PIO3_4 13 [2] PIO3_5 [5] XTALIN 4 [5] XTALOUT [1] See Figure 27 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
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... The LPC1111/12/13/14 contain 32 kB (LPC1114 (LPC1113 (LPC1112 (LPC1111) of on-chip flash memory. 7.3 On-chip SRAM The LPC1111/12/13/14 contain a total of 8 kB on-chip static RAM memory. 7.4 Memory map The LPC1111/12/13/14 incorporates several distinct memory regions, shown in the following figures. ...
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... SRAM (LPC1111/12/13/14/201 SRAM (LPC1111/12/101) reserved 32 kB on-chip flash (LPC1114 on-chip flash (LPC1113 on-chip flash (LPC1112 on-chip flash (LPC1111 (1) LQFP48/PLCC44 packages only. Fig 5. LPC1111/12/13/14 memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts ...
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... NXP Semiconductors • In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupts including inputs to the start logic from individual GPIO pins. • Four programmable interrupt priority levels, with hardware priority level masking. • Relocatable vector table. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags ...
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... Support for modem control. 7.9 SPI serial I/O controller The LPC1111/12/13/14 contain two SPI controllers on the LQFP48/PLCC44 packages and one SPI controller on the HVQFN33 packages (SPI0). Both SPI controllers support SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus ...
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... Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I • The I 7.11 10-bit ADC The LPC1111/12/13/14 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.11.1 Features • 10-bit successive approximation ADC. • Input multiplexing among 8 pins. ...
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... LPC1111_12_13_14_1 Product data sheet × 256 × cy(WDCLK) × 4. cy(WDCLK) All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller × 2 × cy(WDCLK) © NXP B.V. 2010. All rights reserved ...
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... Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC1111/12/13/14 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency ...
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... NXP Semiconductors Upon power-up or any chip reset, the LPC1111/12/13/14 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.15.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... Deep-sleep mode to obtain short wake-up times when waking up from deep-sleep. 7.15.5.3 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1111/12/13/14 can wake up from Deep power-down mode via the WAKEUP pin. 7.16 System control 7.16.1 Reset Reset has four sources on the LPC1111/12/13/14: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit ...
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... Code security (Code Read Protection - CRP) This feature of the LPC1111/12/13/14 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...
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... Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC1111_12_13_14_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... DD I (1. < 125 ° based on package heat transfer, not device power consumption human body model; all pins All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller Min Max 1.8 3.6 −0.5 [2] +5.5 [3] - 100 [3] - 100 - 100 − ...
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... OH 1.8 V ≤ V [13] < 2 − 2.0 V ≤ V ≤ 3.6 V; [13 1.8 V ≤ V [13] < 2 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller [1] Min Typ Max 1.8 3.3 3 220 - - 0 ...
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... − 0 ≥ 2.0 V ≤ V ≤ 3 1.8 V ≤ V < 2 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller [1] Min Typ Max −4 [13 −3 [13 [13 [13 −45 [14] ...
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... C-bus pins OL configured as Fast-mode Plus pins 2.0 V ≤ V ≤ 3 1.8 V ≤ V < 2 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller [1] Min Typ Max −45 [14 [14 150 −15 −50 − ...
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... Figure 7. Figure Figure 7. = 4.5 MHz and analog input capacitance C s × All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller = 2 3 Min Typ [1][ [3] ...
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... Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ) IA ideal ). D ). All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller (1) 1018 1019 1020 1021 1022 1023 − LSB = 1024 offset gain error error E E ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller Min Typ Max - ...
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... AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. Active mode: Typical supply current I clock frequencies All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller (2) 48 MHz (2) 36 MHz ...
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... Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0xFFFF FDFF). supply voltages V DD All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller (2) 48 MHz (2) 36 MHz (2) 24 MHz ...
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... Conditions 3 pin PIO0_7. DD output current All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller VDD = 3.6 V 3.3 V 2 temperature (°C) versus temperature for versus HIGH-level ...
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... 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 002aaf019 °C 25 °C −40 °C 0.4 V (V) OL 002aae991 °C 25 °C −40 °C ...
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... Conditions 3.3 V; standard port pins. DD versus input voltage V pu All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 16 I (mA) OH versus HIGH-level output source current 002aae992 ...
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... Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller versus input voltage V I 002aae989 5 V (V) I © NXP B.V. 2010. All rights reserved. ...
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... Conditions oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time t CHCL All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller Min Typ Max [1] 10000 - - ...
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... Dynamic characteristics: Watchdog oscillator Conditions internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller [1] Conditions Min Typ 11. temperature (° ...
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... Fast-mode Fast-mode Plus 2 C-bus specification UM10204 for details. is the data hold time that is measured from the falling edge of SCL; applies to data in transmission All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller [1] Min Typ 3 ...
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... SPI mode 0 [2] - [2] 0 [3][4] in SPI mode 0 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller ) of the SCL signal. If the clock stretches the SCL, the LOW 2 C-bus system but the requirement t t VD;DAT t HIGH 70 % ...
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... DATA VALID MOSI DATA VALID MISO Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller Typ Max + cy(PCLK) 3 × ...
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... DATA VALID t v(Q) MISO DATA VALID Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller t t clk(H) clk( ...
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... The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1111/12/13/14 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • ...
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... Crystal load capacitance C OSC All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 002aaf424 /C in oscillation mode (crystal and external X2 Maximum crystal ...
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... I/O pins with analog input function: output enable output driver repeater mode enable pull-down enable data input analog input All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller and C should be chosen smaller weak pull-up pull-up enable ...
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... NXP Semiconductors 11.5 Reset pad configuration Fig 27. Reset pad configuration LPC1111_12_13_14_1 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller ESD ESD V SS 002aaf274 © ...
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... 0.27 0.18 7.1 7.1 9.15 9.15 0.5 0.17 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller detail 0.75 0.95 1 0.2 0.12 0.1 0.45 0.55 EUROPEAN PROJECTION SOT313-2 ...
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... REFERENCES JEDEC JEITA MS-018 EDR-7319 All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller detail ...
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... 7.1 4.85 7.1 4.85 7.0 4.70 7.0 4.70 0.65 4.55 4.55 6.9 4.55 6.9 4.55 References JEDEC JEITA - - - All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller detail 0.75 0.60 0.1 0.05 0.08 0.1 0.45 European projection c hvqfn33_po Issue date ...
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... Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... Release date LPC1111_12_13_14_1 20100416 LPC1111_12_13_14_1 Product data sheet Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller Change notice Supersedes - © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors’ warranty of the All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 April 2010 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC1111_12_13_14_1 All rights reserved. Date of release: 16 April 2010 ...