P89LPC9151 NXP [NXP Semiconductors], P89LPC9151 Datasheet - Page 50

• Manufacturer Part Number: P89LPC9151
• Description: 8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
P89LPC9151_61_71_2
Product data sheet
7.21.4 Mode 3
7.21.5 Baud rate generator and selection
7.21.6 Framing error
7.21.7 Break detect
7.21.8 Double buffering
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9
bit is not saved. The baud rate is programmable to either
frequency, as determined by the SMOD1 bit in PCON.
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the baud rate generator (described in
Section 7.21.5 “Baud rate generator and
The P89LPC9151/9161/9171 enhanced UART has an independent baud rate generator.
The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar manner
as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent baud rate generators use OSCCLK.
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up
when SMOD0 is logic 0.
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Fig 12. Baud rate sources for UART (Modes 1, 3)
baud rate generator
timer 1 overflow
(CCLK-based)
(PCLK-based)
th
data bit goes into RB8 in special function register SCON, while the stop
Rev. 02 — 9 February 2010
÷2
SMOD1 = 1
SMOD1 = 0
th
P89LPC9151/9161/9171
data bit, and a stop bit (logic 1). In fact, Mode 3 is
selection”).
8-bit microcontroller with 8-bit ADC
SBRGS = 0
SBRGS = 1
1
⁄
16
or
baud rate modes 1 and 3
1
⁄
32
of the CPU clock
© NXP B.V. 2010. All rights reserved.
Figure
002aaa897
12). Note
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