P89LPC9151 NXP [NXP Semiconductors], P89LPC9151 Datasheet - Page 29

• Manufacturer Part Number: P89LPC9151
• Description: 8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC
• Manufacturer: NXP [NXP Semiconductors]

Table 8.
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
Name
TCON*
TH0
TH1
TL0
TL1
TMOD
TRIM
WDCON
WDL
WFEED1
WFEED2
All ports are in input only (high-impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC9161 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on
reset value is x011 0000.
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
Special function registers - P89LPC9161
Description
Timer 0 and 1
control
Timer 0 high
Timer 1 high
Timer 0 low
Timer 1 low
Timer 0 and 1
mode
Internal
oscillator trim
register
Watchdog
control register
Watchdog load
Watchdog
feed 1
Watchdog
feed 2
Bit address
SFR
addr.
8CH
8DH
C1H
C2H
C3H
88H
8AH
8BH
89H
96H
A7H
Bit functions and addresses
T1GATE
RCCLK
PRE2
MSB
TF1
8F
T1C/T
PRE1
TR1
8E
-
TRIM.5
T1M1
PRE0
TF0
8D
TRIM.4
T1M0
TR0
8C
-
T0GATE
TRIM.3
8B
-
-
WDRUN
TRIM.2
T0C/T
8A
-
WDTOF
TRIM.1
T0M1
IE0
89
WDCLK
TRIM.0
T0M0
LSB
IT0
88
Reset value
Hex
00
00
00
00
00
00
[5][6]
[4][6]
FF
Binary
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111