AT32UC3A0512-ALTES ATMEL [ATMEL Corporation], AT32UC3A0512-ALTES Datasheet - Page 35

• Manufacturer Part Number: AT32UC3A0512-ALTES
• Description: AVR32 32-Bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

10.11.4
10.11.5
10.11.6
10.11.7
32058FS–AVR32–08/08
USB Controller
Serial Peripheral Interface
Two-wire Interface
USART
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Error Detection
SDRAM Power-up Initialization by Software
CAS Latency of 1, 2, 3 Supported
Auto Precharge Command Not Used
USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s
7 Pipes/Endpoints
960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels
On-Chip Transceivers Including Pull-Ups
Supports communication with serial external devices
Master or slave serial peripheral bus interface
Very fast transfers supported
High speed up to 400kbit/s
Compatibility with standard two-wire serial memory
One, two or three bytes for slave address
Sequential read/write operations
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
– Supports Mobile SDRAM Devices
– Refresh Error Interrupt
– Four chip selects with external decoder support allow communication with up to 15
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
– External co-processors
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock and data
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Transfers with baud rates up to Peripheral Bus A (PBA) max frequency
– The chip select line may be left active to speed up transfers on the same device
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
peripherals
per chip select
AT32UC3A
35