ATMEGA644PV ATMEL [ATMEL Corporation], ATMEGA644PV Datasheet - Page 237
ATMEGA644PV
Manufacturer Part Number
ATMEGA644PV
Description
8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA644PV.pdf
(408 pages)
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20.3.3
8011D–AVR–02/07
DIDR1 – Digital Input Disable Register 1
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly connected to the
input capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection
between the Analog Comparator and the input capture function exists. To make the comparator
trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
• Bits 1:0 – ACIS1:ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in
Table 20-2.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
• Bit 1:0 – AIN1D:AIN0D: AIN1:AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
Bit
(0x7F)
Read/Write
Initial Value
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
R
7
–
0
ACIS0
0
1
0
1
R
6
–
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table
R
5
–
0
20-2.
R
4
–
0
ATmega164P/324P/644P
R
3
–
0
R
2
–
0
AIN1D
R/W
1
0
AIN0D
R/W
0
0
DIDR1
237
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