ATMEGA644PV ATMEL [ATMEL Corporation], ATMEGA644PV Datasheet - Page 14

• Manufacturer Part Number: ATMEGA644PV
• Description: 8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

5.5.1
5.5.2
5.6
14
Instruction Execution Timing
ATmega164P/324P/644P
SPH and SPL – Stack Pointer High and Stack pointer Low
RAMPZ – Extended Z-pointer Register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 5-4. Note that LPM is not affected by the RAMPZ setting.
Figure 5-4.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 5-5 on page 15
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Bit
0x3B (0x5B)
Read/Write
Initial Value
Bit (
Individually)
Bit (Z-pointer)
The Z-pointer used by ELPM and SPM
RAMPZ7
R/W
R/W
SP7
15
R
7
0
–
7
0
1
23
7
shows the parallel instruction fetches and instruction executions enabled
RAMPZ6
R/W
SP6
R/W
RAMPZ
14
6
0
R
–
6
0
1
RAMPZ5
R/W
SP5
R/W
CPU
5
0
13
R
–
5
0
1
16
0
, directly generated from the selected clock source for the
RAMPZ4
R/W
SP12
R/W
R/W
SP4
4
0
12
4
1
1
15
7
RAMPZ3
R/W
SP11
SP3
R/W
R/W
3
0
11
3
0
1
ZH
RAMPZ2
R/W
SP10
2
0
SP2
R/W
R/W
10
2
0
1
0
8
RAMPZ1
R/W
R/W
R/W
SP9
SP1
1
0
9
1
0
1
7
7
RAMPZ0
R/W
SP8
SP0
R/W
R/W
0
0
8
0
0
1
8011D–AVR–02/07
ZL
RAMPZ
SPH
SPL
0
0