ATMEGA48V_06 ATMEL [ATMEL Corporation], ATMEGA48V_06 Datasheet - Page 264

• Manufacturer Part Number: ATMEGA48V_06
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

24.2.1
24.2.2
24.2.3
264
ATmega48/88/168
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
Preventing Flash Corruption
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below.See
a detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown
below. See
byte.
Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an
LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set
in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as
shown below. See
Fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
Bit
Rd
Bit
Rd
Bit
Rd
Bit
Rd
Table 26-4 on page 286
FHB7
FHB7
FLB7
7
–
7
7
7
Table 26-5 on page 287
CC
FHB6
FLB6
FHB6
, the Flash program can be corrupted because the supply voltage is
6
6
–
6
6
FHB5
FHB5
FLB5
5
5
5
5
–
for detailed description and mapping of the Extended Fuse
for detailed description and mapping of the Extended
FHB4
FLB4
FHB4
4
–
4
4
4
FHB3
FHB3
FLB3
3
–
3
3
3
FHB2
FHB2
FLB2
2
–
2
2
2
Table 26-5 on page 287
FHB1
FHB1
FLB1
LB2
1
1
1
1
FHB0
FLB0
FHB0
LB1
0
0
0
0
2545J–AVR–12/06
for