AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 245

no-image

AT90USB1286-16MU

Manufacturer Part Number
AT90USB1286-16MU
Description
Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90USB1286-16MU
Manufacturer:
ST
0
20.9
7593A–AVR–02/06
Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simulta-
neously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
Figure 20-21. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
This is summarized in
• Two or more masters are performing identical communication with the same Slave. In this
• Two or more masters are accessing the same Slave with different data or direction bit. In this
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
case, neither the Slave nor any of the masters will know about the bus contention.
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
SDA
SCL
TRANSMITTER
Device 1
MASTER
Figure
20-22. Possible status values are given in circles.
TRANSMITTER
Device 2
MASTER
Device 3
RECEIVER
SLAVE
........
Device n
V
CC
AT90USB64/128
R1
R2
245

Related parts for AT90USB1286-16MU