AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 179

• Manufacturer Part Number: AT90USB1286-16MU
• Description: Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
• Manufacturer: ATMEL [ATMEL Corporation]

17.1.4
7593A–AVR–02/06
SPI Status Register – SPSR
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 17-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 17-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 17-4.
• Bit 7 – SPIF: SPI Interrupt Flag
Bit
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
0
1
0
1
7
SPIF
R
0
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
Figure 17-3
6
WCOL
R
0
SPR1
0
0
1
1
0
0
1
1
5
–
R
0
and
Leading Edge
Leading Edge
Figure 17-4
Figure 17-3
4
–
R
0
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
3
–
R
0
for an example. The CPOL functionality is sum-
and
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
2
–
R
0
Figure 17-4
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
1
–
R
0
AT90USB64/128
Trailing Edge
Trailing Edge
for an example. The CPOL
Sample
Falling
Rising
Setup
0
SPI2X
R/W
0
SPSR
osc
179
is