AT90PWM2B-16SE ATMEL [ATMEL Corporation], AT90PWM2B-16SE Datasheet - Page 41

• Manufacturer Part Number: AT90PWM2B-16SE
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

8.3
8.4
8.5
4317J–AVR–08/10
ADC Noise Reduction Mode
Power-down Mode
Standby Mode
Watchdog, and the interrupt system to continue operating. This sleep mode basically halt clk
and clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts,
Timer/Counter (if their clock source is external - T0 or T1) and the Watchdog to continue
operating (if enabled). This sleep mode basically halts clk
the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, a Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an External Level Interrupt
on INT3:0 can wake up the MCU from ADC Noise Reduction mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the External Oscillator is stopped, while the External Interrupts and
the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a
Brown-out Reset, a PSC Interrupt, an External Level Interrupt on INT3:0 can wake up the MCU.
This sleep mode basically halts all generated clocks, allowing operation of asynchronous mod-
ules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL fuses that define the
Reset Time-out period, as described in
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
FLASH
, while allowing the other clocks to run.
“Clock Sources” on page
I/O
AT90PWM2/3/2B/3B
, clk
CPU
“External Interrupts” on page 80
30.
, and clk
FLASH
, while allowing
CPU
41