AT90PWM2B-16SE ATMEL [ATMEL Corporation], AT90PWM2B-16SE Datasheet - Page 15

• Manufacturer Part Number: AT90PWM2B-16SE
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

5.8
4317J–AVR–08/10
Reset and Interrupt Handling
Figure 5-4.
Figure 5-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 5-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming” on page 278
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is PSC2 CAPT – the PSC2 Capture
Event. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the
IVSEL bit in the MCU Control Register (MCUCR). Refer to
mation. The Reset Vector can also be moved to the start of the Boot Flash section by
programming the BOOTRST Fuse, see
gramming” on page
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
for details.
264.
clk
clk
CPU
CPU
T1
T1
“Boot Loader Support – Read-While-Write Self-Pro-
T2
T2
AT90PWM2/3/2B/3B
“Interrupts” on page 56
“Interrupts” on page
T3
T3
“Memory Program-
56. The list also
for more infor-
T4
T4
15