AT90PWM2B-16SE ATMEL [ATMEL Corporation], AT90PWM2B-16SE Datasheet - Page 188

• Manufacturer Part Number: AT90PWM2B-16SE
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

18.4.2
18.5
188
USART Initialization
AT90PWM2/3/2B/3B
Parity Bit Calculation
Figure 18-4. Frame Formats
The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB
and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting
of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the
second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first
stop bit is zero.
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
The USART has to be initialized before any communication can take place.
The configuration between the USART or EUSART mode should be done before any other
configuration.
The initialization process normally consists of setting the baud rate, setting frame format and
enabling the Transmitter or the Receiver depending on the usage.
For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and inter-
rupts globally disabled) when doing the initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no
ongoing transmissions during the period the registers are changed. The TXC flag can be used to
check that the Transmitter has completed all transfers, and the RXC flag can be used to check
St
(n)
P
Sp
IDLE
P
P
d
n
even
odd
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxD or TxD). An IDLE line must be
high.
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
(IDLE)
P
St
P
even
odd
0
=
=
d
d
1
n 1
n 1
–
–
2
⊕
⊕
…
…
3
⊕
⊕
d
d
4
3
3
FRAME
⊕
⊕
[5]
d
d
2
2
⊕
⊕
[6]
d
d
1
1
[7]
⊕
⊕
d
d
0
0
[8]
⊕
⊕
0
1
[P]
Sp1 [Sp2]
(St / IDLE)
4317J–AVR–08/10