FAN2106_08 FAIRCHILD [Fairchild Semiconductor], FAN2106_08 Datasheet - Page 10

• Manufacturer Part Number: FAN2106_08
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2006 Fairchild Semiconductor Corporation
FAN2106 Rev. 1.0.8
Circuit Description
Application Note AN-6033 — FAN2106 Design Guide
includes a spreadsheet design aid to calculate external
component values and verify loop stability given the
following inputs:
Download AN-6033 — FAN2106 Design Guide at:
http://www.fairchildsemi.com/an/AN/AN-6033.pdf
Initialization
Once V
HIGH, the IC checks for an open or shorted FB pin
before releasing the internal soft-start ramp (SS).
If R1 is open (Figure 1), the error amplifier output
(COMP) is forced LOW and no pulses are generated.
After the SS ramp times out (T1.0), an under-voltage
latched fault occurs.
If the parallel combination of R1 and R
internal SS ramp is not released and the regulator does
not start.
Soft-Start
Once internal SS ramp has charged to 0.8V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0V (T1.0), the “Fault Latch” is inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply V
Soft-start time is a function of oscillator frequency.
Output voltage
Input voltage range
Maximum output load current
Maximum load transient current and maximum
allowable output drop during load transient
Maximum allowable output ripple
Desired switching frequency
IN
EN
FB
SS
CC
Figure 21. Soft-Start Timing Diagram
before V
exceeds the UVLO threshold and EN is
CC
1.35V
reaches its UVLO threshold.
3200 CLKs
4000 CLKs
2400 CLKs
1.0V
0.8V
T0.8
T1.0
BIAS
Fault
Latch
Enable
0.8V
is ≤ 1KΩ, the
10
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until
internal SS ramp reaches 95% of V
helps the regulator to start on a pre-biased output and
ensures that inductor current does not "ratchet" up
during the soft-start cycle.
V
resets the IC.
Bias Supply
The FAN2106 requires a 5V supply rail to bias the IC
and provide gate-drive energy. Connect a ≥ 1.0µf X5R
or X7R decoupling capacitor between VCC and PGND.
Since V
supply current is frequency and voltage dependent.
Approximate V
where frequency (f) is expressed in KHz.
Setting the Output Voltage
The output voltage of the regulator can be set from 0.8V
to 80% of V
R
The internal reference is 0.8V with 650nA, sourced from
the FB pin to ensure that, if the pin is open, the
regulator does not start.
The external resistor divider is calculated using:
Connect R
Setting the Frequency
Oscillator frequency is determined by an external resistor,
R
where R
where frequency (f) is expressed in KHz.
The regulator can not start if R
I
R
f
R
CC
0
(
CC
T,
BIAS
KHz
BIAS
T
8 .
(
connected between the R(T) pin and AGND:
K (
mA
UVLO or toggling the EN pin discharges the SS and
V
)
Ω
in Figure 1).
=
)
)
=
=
=
CC
(
T
65
V
. 4
(
is expressed in KΩ.
10
OUT
BIAS
is used to drive the internal MOSFET gates,
58
•
IN
6
R
10
R
between FB and AGND.
CC
/
+
−
by an external resistor divider (R1 and
65
1
T
) f
0
[(
6
)
current (I
8 .
−
+
V
135
V
135
CC
227
+
−
650
5
CC
+
nA
) can be calculated using:
. 0
T
013
is left open.
)
•
REF
f (
−
(~0.76V). This
128
www.fairchildsemi.com
)]
(1)
(2)
(3)
(4)