FAN2103_08 FAIRCHILD [Fairchild Semiconductor], FAN2103_08 Datasheet - Page 12

• Manufacturer Part Number: FAN2103_08
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.5
Under-Voltage Shutdown
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
Over-Voltage Protection / Shutdown
If FB exceeds 115%
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The two fault protection circuits above are active all the
time, including during soft-start.
Auto-Restart
After a fault, EN is discharged with 1µA to a 1.1V
threshold before the 800KΩ pull-up is restored. A new
soft-start cycle begins when EN charges above 1.35V.
Depending on the external circuit, the FAN2103 can be
provisioned to remain latched-off or automatically
restart after a fault.
Table 1. Fault / Restart Provisioning
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC
pin or pull it high after V
keep the 1µA current sink from discharging EN to 1.1V.
Figure 24.
EN pin
Pull to GND
V
Open
Cap to GND
CC
Fault Latch with Delayed Auto-Restart
Controller / Restart State
OFF (disabled)
No restart – latched OFF (after V
comes up)
Immediate restart after fault
New soft-start cycle after:
t
DELAY
•
CC
V
(ms) = 3.9
REF
comes up with a logic gate to
for two consecutive clock
•
C(nf)
CC
12
Over-Temperature Protection
FAN2103 incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 160°C is reached. The IC is allowed to restart
when the die temperature falls below 130°C.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW
when V
pin
Specifications section). PGOOD does not assert HIGH
until the fault latch is enabled (T1.0).
PCB Layout
(thresholds
Figure 25. Recommended PCB Layout
OUT
is out of regulation, as measured at the FB
are
specified
in
the
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