FDMF3030 FAIRCHILD [Fairchild Semiconductor], FDMF3030 Datasheet - Page 12

• Manufacturer Part Number: FDMF3030
• Description: Extra-Small, High-Performance, High-Frequency, DrMOS Module
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2012 Fairchild Semiconductor Corporation
FDMF3030 • Rev. 1.0.0
THWN#
Logic
State
Functional Description
The FDMF3030 is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1MHz.
VCIN and Disable (DISB#)
The VCIN pin is monitored by an Under-Voltage Lockout
(UVLO) circuit. When V
is enabled. When V
disabled (GH, GL=0). The driver can also be disabled by
pulling the DISB# pin LOW (DISB# < V
holds both GL and GH LOW regardless of the PWM
input state. The driver can be enabled by raising the
DISB# pin voltage HIGH (DISB# > V
Table 1.
Note:
3.
Thermal Warning Flag (THWN#)
The FDMF3030 provides a thermal warning flag
(THWN#) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN# output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN# output
requires a pull-up resistor, which can be connected to
VCIN. THWN# does NOT disable the DrMOS module.
UVLO DISB#
0
1
1
1
DISB# internal pull-down current source is 10µA.
HIGH
LOW
Open
UVLO and Disable Logic
Figure 28.
X
0
1
Normal
Operation
135°C Reset
Temperature
CIN
T
CIN
falls below ~2.95V, the driver is
J_driver IC
THWN Operation
Enabled (see Table 2)
rises above ~3.3V, the driver
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Driver State
150°C
Activation
Temperature
IH_DISB
).
Thermal
Warning
IL_DISB
), which
12
Three-State PWM Input
The FDMF3030 incorporates a three-state 5V PWM
input gate drive design. The three-state gate drive has
both logic HIGH level and LOW level, along with a
three-state shutdown window. When the PWM input
signal enters and remains within the three-state window
for a defined hold-off time (t
are pulled LOW. This enables the gate drive to shut
down both high-side and low-side MOSFETs to support
features such as phase shedding, which is common on
multi-phase voltage regulators.
Exiting Three-State Condition
When
FDMF3030 follows the PWM input command. If the
PWM input goes from three-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from
three-state to HIGH, the high-side MOSFET is turned
on. This is illustrated in Figure 29. The FDMF3030
design allows for short propagation delays when exiting
the three-state window (see Electrical Characteristics).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced, low-R
for GL is internally connected between the VDRV and
CGND pins. When the driver is enabled, the driver's
output is 180° out of phase with the PWM input. When
the driver is disabled (DISB#=0V), GL is held LOW.
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstrap capacitor (C
at PGND, allowing C
internal diode. When the PWM input goes HIGH, GH
begins to charge the gate of the high-side MOSFET
(Q1). During this transition, the charge is removed from
C
V
which provides sufficient V
complete the switching cycle, Q1 is turned off by pulling
GH to V
falls to PGND. GH output is in-phase with the PWM
input. The high-side gate is held LOW when the driver is
disabled or the PWM signal is held within the three-state
window for longer than the three-state hold-off time,
t
D_HOLD-OFF
SWH
BOOT
rises to V
and delivered to the gate of Q1. As Q1 turns on,
SWH
exiting
.
. C
BOOT
IN
, forcing the BOOT pin to V
a
DS(ON)
is then recharged to V
valid
BOOT
BOOT
, N-channel MOSFET. The bias
to charge to V
). During startup, V
GS
D_HOLD-OFF
three-state
enhancement for Q1. To
), both GL and GH
DRV
condition,
DRV
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through the
when V
SWH
IN
+ V
is held
BOOT
SWH
the
,