MT28F320J3FS-12 MICRON [Micron Technology], MT28F320J3FS-12 Datasheet - Page 34
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MT28F320J3FS-12
Manufacturer Part Number
MT28F320J3FS-12
Description
Q-FLASHTM MEMORY
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT28F320J3FS-12.pdf
(52 pages)
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128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
CLEAR BLOCK LOCK BITS Flowchart
FULL STATUS CHECK PROCEDURE
Read Status Register
CLEAR BLOCK LOCK
CLEAR BLOCK LOCK
Data (see above)
Check if Desired
BITS Successful
BITS Complete
Read Status
Full Status
Write D0h
Write 60h
Register
SR4,5 =
SR3 =
SR7 =
SR5 =
Start
1
0
0
0
Figure 10
0
1
1
1
Voltage Range Error
Command Sequence
CLEAR BLOCK LOCK
BITS Error
Error
34
BUS
OPERATION COMMAND
WRITE
WRITE
READ
STANDBY
BUS
OPERATION COMMAND
STANDBY
STANDBY
STANDBY
Write FFh after the CLEAR BLOCK LOCK BITS operation to
place device in read array mode.
SR5, SR4, and SR3 are only cleared by the CLEAR STATUS
REGISTER command.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CLEAR
BLOCK LOCK Addr = X
BITS SETUP
CLEAR BLOCK Data = D0h
LOCK BITS
or CONFIRM
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
COMMENTS
Data = 60h
Addr = X
Status Register Data
Check SR7
1 = ISM Ready
0 = ISM Busy
COMMENTS
Check SR3
1 = Programming Voltage
Check SR4, 5
Both 1 = Command
Check SR5
1 = Clear Block Lock Bits
Error Detect
Error
Sequence Error
©2002, Micron Technology, Inc.
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