MT28F320J3FS-12 MICRON [Micron Technology], MT28F320J3FS-12 Datasheet
MT28F320J3FS-12
Related parts for MT28F320J3FS-12
MT28F320J3FS-12 Summary of contents
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... Operating Temperature Range Commercial Temperature (0ºC to +85ºC) Extended Temperature (-40ºC to +85ºC) 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S ...
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... JEDEC ID-independent with forward and backward compatibility. Additionally, the scalable command set (SCS) al- lows a single, simple software driver in all host systems to work with all SCS-compliant Flash memory devices. The SCS provides the fastest system/device data trans- fer rates and minimizes the device and system-level implementation costs. ...
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... DEVICE MARKING Due to the size of the package, Micron’s standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a Cross Reference for Abbreviated Device Marks PART NUMBER MT28F320J3FS-11 MT28F320J3FS-11 ET MT28F640J3FS-12 MT28F640J3FS-12 ET MT28F128J3FS-15 MT28F128J3FS-15 ET 56-Pin TSOP Type I 1 ...
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... I/O Control Logic A0–A22 CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 FUNCTIONAL BLOCK DIAGRAM (128Mb) Addr. Buffer/ Latch Addr. Power (Current) Counter Control State Y - Machine Decoder V PP Switch/ Pump ...
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... I/O Control Logic A0–A21 CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 FUNCTIONAL BLOCK DIAGRAM (32Mb) Addr. Buffer/ Latch Addr. Power (Current) Counter Control State Y - Machine Decoder V PP Switch/ Pump ...
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... WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL the memory array. Addresses and data are latched on the rising edge of the WE# pulse. CE0, CE1, Input Chip Enable: Three CE pins enable the use of multiple ...
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... H3, A6 21, 42, 48 B2, H4 – B6, C6, D5, D6, E6, F6, F7, H2 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 SYMBOL TYPE V Q Supply V Q controls the output voltages. To obtain output CC CC voltage compatible with system data bus voltages, connect the system supply voltage ...
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... A0–A23: 128Mb A0–A22: 64Mb A0–A21: 32Mb Byte-Wide (x8) Mode BUS OPERATION All bus cycles to and from the Flash memory must conform to the standard microprocessor bus cycles. The local CPU reads and writes Flash memory in- system. READ Information can be read from any block, query, iden- tifier codes, or status register, regardless of the V voltage ...
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... Flash memory. During block erase, program, or lock bit configuration mode, automated Flash memo- ries provide status information when accessed. When a CPU reset occurs with no Flash memory reset, proper initialization may not occur because the Flash memory may be providing status information instead of array data ...
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... IL IH Enabled Enabled ≤ memory contents can be read, but not altered. PEN PENLK or V PENLK when the ISM is executing internal block erase, program, or lock bit configuration during a WRITE operation 128Mb, 64Mb, 32Mb Q-FLASH MEMORY STS DEFAULT 3 ...
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... When the V voltage is less than V PEN operations from the status register, query, identifier codes, or blocks are enabled. Placing V ables BLOCK ERASE, PROGRAM, and LOCK BIT CON- Micron Q-Flash Memory Command Set Definitions COMMAND SCALABLE OR BASIC COMMAND REQ’D SET READ ARRAY ...
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... X = Any valid address within the device BA = Address within the block IA = Identifier code address; see Figure 2 and Table Query data base address PA = Address of memory location to be programmed Data read from identifier codes QD = Data read from query data base SRD = Data read from status register; see Table 16 for a description of the status register bits PD = Data to be programmed at location PA ...
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... NOTE: 1. The system must drive the lowest-order addresses to access all the device’s array data when the device is configured in x8 mode. Therefore, word addressing where these lower addresses are not toggled by the system is “Not Applicable” for x8-configured devices. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 QUERY STRUCTURE OUTPUT The query “ ...
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... BA = Block address beginning location (i.e., 020000h is block two’s beginning location when the block size is 64K-word). 3. Offset 15 defines “P,” which points to the Primary Extended Query Table. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 6 ...
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... Secondary algorithm extended query table address; 0000h means none exists 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 tionally, it indicates the specification version and sup- ported vendor-specified command set(s). Table 8 Block Status Register ...
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... Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 10 System Interface Information n µs 16 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ...
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... Partition size = (total blocks) x (individual block size) 2Dh 4 Erase Block Region 1 Information Bits 0– number of identical-size erase blocks Bits 16– region erase block(s) size are z x 256 bytes 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 11a Device Geometry Definitions n in number of bytes ...
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... Bits 0–3 BCD value in 100mV Bits 4–7 Hex value in volts NOTE: 1. Future devices may not support the described “Legacy Lock/Unlock” function. On these devices, bit 3 would have a value of “0.” 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ...
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... Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (P+15)h Reserved for future use. NOTE: 1. The variable “P” pointer which is defined at CFI offset 15h. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 13 Protection Register Information n ...
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... The lowest-order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h selects the specific block’s lock configuration code. See Figure 2 for the device identifier code memory map. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 erasure, or lock bit configuration ...
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... SR2 = PROGRAM SUSPEND STATUS (PSS Program Suspended 0 = Program in Progress/Completed Yes SR1 = DEVICE PROTECT STATUS (DPS Block Lock Bit Detected, Operation Aborted 0 = Unlock Yes SR0 = RESERVED FOR FUTURE ENHANCEMENTS 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 16 Status Register Definitions ECLBS PSLBS V PENS 5 ...
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... BLOCK ERASE SUSPEND COMMAND The BLOCK ERASE SUSPEND command allows block erase interruption in order to read or program data in another block of memory. Writing the BLOCK ERASE SUSPEND command immediately after start- ing the block erase process requests that the ISM sus- pend the block erase sequence at an appropriate point in the algorithm ...
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... READ QUERY, READ STATUS REGIS- TER, CLEAR STATUS REGISTER, CONFIGURE, and BLOCK ERASE RESUME. After a BLOCK ERASE RESUME command to the Flash memory is completed, the ISM continues the block erase process. Status register bits SR6 and SR7 automatically clear and STS (in default mode) returns to V ...
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... Refer to Figure 6 (PROGRAM SUSPEND/RESUME Flowchart). SET READ CONFIGURATION COMMAND Q-Flash memory does not support the SET READ CONFIGURATION command. The devices default to the asynchronous page mode. If this command is given, the operation of the device will not be affected. ...
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... DQ3 RESERVED Used to control HOLD to a memory controller to prevent accessing a Flash memory subsystem while any Flash device’s ISM is busy. Used to generate a system interrupt pulse when any Flash device in an array has completed a BLOCK ERASE or sequence of queued BLOCK ERASEs; helpful for reformatting blocks after file system free space reclamation or “ ...
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... CLEAR BLOCK LOCK BITS is required. PROTECTION REGISTER PROGRAM COMMAND The 3V Q-Flash memory includes a 128-bit protec- tion register to increase the security of a system design. For example, the number contained in the protection register can be used for the Flash component to com- municate with other system components, such as the CPU or ASIC, to prevent device substitution ...
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... B User C User D User E User F User NOTE: 1. All address lines not specified in the above tables must be “0” when accessing the protection register (i.e., A22–A9 = 0). 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table ...
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... The status register indicates an “improper command sequence” if the WRITE-to-BUFFER command is aborted. Follow this with a CLEAR STATUS REGISTER command. 7. Toggling OE# (LOW to HIGH to LOW) updates the status register. This can be done in place of issuing the READ STATUS REGISTER command. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND ...
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... SR3 = 0 1 SR1 = Device Protect Error 0 1 Programming Error SR4 = 0 Byte/Word Program Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 128Mb, 64Mb, 32Mb Q-FLASH MEMORY BUS OPERATION COMMAND COMMENTS WRITE SETUP BYTE/ Data = 40h WORD Addr = Location to be PROGRAM ...
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... SR7 = 1 0 SR2 = 1 Write FFh Read Data Array 1 No Done Reading Yes Write D0h Programming Resumed 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE READ STANDBY STANDBY WRITE Programming READ Completed WRITE Write FFh Read Data Array ...
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... Block Address Read Status Register No SR7 = Suspend Erase 1 Full Status Check if Desired Erase Flash Block(s) Complete 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY Suspend No Erase Loop The erase confirm byte must follow erase setup. ...
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... Read Read or Program Program? Read Array Program No Data Loop Done? Yes Write D0h BLOCK ERASE Resumed 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE READ STANDBY STANDBY WRITE BLOCK ERASE Completed Write FFh Read Data Array 32 ...
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... Command Sequence SR4 SET BLOCK LOCK BITS SR4 = 0 SET BLOCK LOCK BITS Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY Repeat for subsequent lock bit operations. Full status check can be done after each lock bit set ...
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... Command Sequence SR4 CLEAR BLOCK LOCK SR5 = 0 CLEAR BLOCK LOCK BITS Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY Write FFh after the CLEAR BLOCK LOCK BITS operation to place device in read array mode. ...
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... PROTECTION REGISTER SR1, SR4 = PROGRAMMING Error Attempted Program SR1, SR4 = Locked Register – PROGRAM Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY PROTECTION PROGRAM operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error ...
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... To efficiently use these control inputs, an address decoder should enable the device (see Table 2) while OE# is connected to all memory devices and the system’s READ# control line. This ensures that only selected memory devices have active outputs while deselected memory devices are in standby mode ...
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... V kept at or above V After block erase, program, or lock bit configuration, and after V placed in read array mode via the READ ARRAY com- mand if subsequent access to the memory array is de- sired. During V below V CC POWER-UP/DOWN PROTECTION During power transition, the device itself provides protection against accidental block erasure, program- ming, or lock bit configuration ...
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... Output Short Circuit Current ............................. 100mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ...
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... NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). 2. Sampled, not 100% tested. 3. Includes STS. 4. MT28F320J3RG-11 F and MT28F640J3RG-12 F only. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ ...
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... PENLK 7. Typically connected to V PEN 8. Block erase, programming, and lock bit configurations are inhibited when V the range between V (MIN) and V LKO 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ CONDITIONS = V (MAX Device is enabled ...
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... Typically connected to V PEN 8. Block erase, programming, and lock bit configurations are inhibited when V the range between V (MIN) and V LKO 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ CONDITIONS CMOS inputs PEN ...
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... Input V 0.0 NOTE: AC test inputs are driven (50 Q). Input rise and fall times (10% to 90%) < 5ns. CC Transient Equivalent Testing Load Circuit 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Figure 2.7V–3.6V Q/2 Test Points CC Q for a logic 1 and 0.0V for a logic 0. Input timing begins, and output timing ends ...
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... See Figures 12 and 13, Transient Input/Output Reference Waveform for V Transient Equivalent Testing Load Circuit for testing characteristics. 5. When reading the Flash array, a faster DEVICE IDENTIFIER READs. 6. Sampled, not 100% tested. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ SYMBOL ...
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... RWH (32Mb) NOTE: CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first edge of CE0, CE1, or CE2 that disables the device. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/ VALID VALID ...
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... AA is required in addition to 9. STS timings are based on STS configured in its RY/BY# default mode. 10. V should be held at V PEN PENH 0). 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ WPH ( and D for block erase, program, or lock bit configuration. ...
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... These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time is 4.7µs/byte (typical). 7. Effective per-word program time is 9.4µs/word (typical). 8. MAX values are measured at worst-case temperature and V 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ ...
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... Write block erase, write buffer, or program setup. 4. Write block erase or write buffer confirm, or valid address and data. 5. Automated erase delay. 6. Read status register or query data. 7. WRITE READ ARRAY command. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 WRITE OPERATIONS Note 3 Note 4 ...
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... CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#). 2. Erase resume, or program resume. 3. Read status, erase suspend or program suspend. 4. STS value will be: V after ERASE SUSPEND and PROGRAM SUSPEND commands IH V after READ STATUS command IL 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 RESUME OPERATIONS Note ...
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... If RP# is asserted while a BLOCK ERASE, PROGRAM, or LOCK BIT CONFIGURATION operation is not executing, then the minimum required RP# pulse LOW time is 100ns reset time, PHQV, is required from the latter of STS (in RY/BY# mode) or RP# going HIGH until outputs are valid. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ SYMBOL ...
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... PIN #1 INDEX +0.03 0.15 -0.02 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 56-PIN TSOP TYPE I 20.00 ±0.10 18.40 ±0.08 14.00 ±0.08 SEE DETAIL A 1.20 MAX 50 128Mb, 64Mb, 32Mb ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the Micron and M logos and Q-Flash are trademarks and/or servicemarks of Micron Technology, Inc. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 64-BALL FBGA 7 ...
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... Removed Block Erase Status bit Rev. 3 ......................................................................................................................................................................................... 6/01 • Updated package drawing and corresponding notes Rev. 2 ......................................................................................................................................................................................... 5/01 • Added 128Mb device information • Added 64-ball FBGA (1.0mm pitch) package Original document, Rev. 1 .................................................................................................................................................. 12/00 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/ ...