IS41C4100-35T ICSI [Integrated Circuit Solution Inc], IS41C4100-35T Datasheet - Page 19
![no-image](/images/no-image-200.jpg)
IS41C4100-35T
Manufacturer Part Number
IS41C4100-35T
Description
1Mx4 bit Dynamic RAM with EDO Page Mode
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
1.IS41C4100-35T.pdf
(21 pages)
- Current page: 19 of 21
- Download datasheet (301Kb)
HIDDEN REFRESH CYCLE
IC41C4100
IC41LV4100
CBR REFRESH CYCLE
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. t
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
OFF
is referenced from rising edge of RAS or CAS, whichever occurs last.
ADDRESS
RAS
CAS
I/O
RAS
CAS
OE
I/O
t
RPC
t
CP
t
t
ASR
CRP
(Addresses; WE, OE = DON'T CARE)
Row
t
RP
(1)
t
CHR
(WE = HIGH; OE = LOW)
t
t
t
RAH
RAD
CSR
t
RCD
Open
t
t
ASC
RAS
t
RAS
t
AR
t
RPC
Column
t
CLZ
t
t
RAC
RAL
t
OE
Open
t
AA
t
CAC
t
CAH
t
RP
t
RSH
t
ORD
t
RP
t
CSR
Valid Data
t
RAS
t
RAS
t
t
CHR
CHR
t
OFF
(2)
Undefined
Don’t Care
Open
t
OD
19
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