IS41C4100-35T ICSI [Integrated Circuit Solution Inc], IS41C4100-35T Datasheet - Page 10

• Manufacturer Part Number: IS41C4100-35T
• Description: 1Mx4 bit Dynamic RAM with EDO Page Mode
• Manufacturer: ICSI [Integrated Circuit Solution Inc]

IC41C4100
IC41LV4100
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
2. V
3. In addition to meeting the transition rate specification, all input signals must transit between V
4. If CAS and RAS = V
5. If CAS = V
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
8. Assumes that t
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
10. Operation with the t
11. Operation within the t
12. Either t
13. t
14. t
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
19. The I/Os are in open during READ cycles once t
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless CAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
10
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
and V
in a monotonic manner.
by the amount that t
data output buffer, CAS and RAS must be pulsed for t
is greater than the specified t
is greater than the specified t
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
(MIN), t
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to V
WRITE or READ-MODIFY-WRITE is not possible.
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after t
MODIFY-WRITE cycles.
OFF
WCS
IH
(MIN) and V
IH
, t
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
IL
RWD
RCH
AWD
(or between V
, t
IL
or t
AWD
≥ t
, data output may contain data from the last valid READ cycle.
RRH
AWD
RCD
RCD
and t
IL
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
must be satisfied for a READ cycle.
≥ t
≤ t
(MIN) and t
RCD
RCD
IH
CWD
RAD
RCD
, data output is High-Z.
IL
RCD
(MAX) limit ensures that t
and V
exceeds the value shown.
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
(MAX) limit ensures that t
(MAX).
(MAX). If t
RCD
RAD
CWD
IH
) and assume to be 1 ns for all inputs.
(MAX) limit, access time is controlled exclusively by t
(MAX) limit, access time is controlled exclusively by t
≥ t
RCD
OEH
CWD
is met.
is greater than the maximum recommended value shown in this table, t
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
OD
RAC
RCD
or t
(MAX) can be met. t
CP
(MAX) can be met. t
OFF
.
occur.
OD
and t
OEH
RCD
RAD
met (OE HIGH during WRITE cycle) in order to ensure
(MAX) is specified as a reference point only; if t
(MAX) is specified as a reference point only; if t
AA
CAC
REF
.
.
Integrated Circuit Solution Inc.
refresh requirement is exceeded.
IH
and V
IL
(or between V
DR027-0A 09/05/2001
OH
RAC
or V
will increase
OL
RWD
WCS
IL
.
and V
≥ t
≥ t
RWD
WCS
RCD
RAD
IH
IH
)