CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 5

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Pin Definitions
Master Reset
The FLEx72 family devices undergo a complete reset by
taking the MRST input LOW. MRST input can switch
asynchronously to the clocks. MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the mailbox
interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx72 family
devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports using 18Mbit
device as an example. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for
the left port. Table 2.shows that in order to set the INT
Table 2. Interrupt Operation Example
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Note:
11. CE is internal signal. CE = LOW if CE
12. OE is “Don’t Care” for mailbox operation.
13. At least one of BE0 or BE7 must be LOW.
the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
Function
Left Port
L
Flag
R
L
Flag
Flag
R
Flag
(continued)
V
TDO
V
TCK
V
TDI
CORE
TTL
SS
R/W
X
X
H
L
Right Port
L
0
= LOW and CE
CE
[1, 11, 12, 13]
X
X
L
L
L
Left Port
1
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK.
TDO is normally three-stated except when captured data is shifted out of the
JTAG TAP.
Ground Inputs.
Core Power Supply.
LVTTL Power Supply.
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of
PRELIMINARY
A
3FFFF
3FFFE
0L–17L
R
X
X
flag, a
INT
write operation by the left port to address 3FFFF will assert
INT
generate an interrupt. A valid Read of the 3FFFF location by
the right port will reset INT
active in order for a read to reset the interrupt. When one port
writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
X
X
H
L
L
R
LOW. At least one byte has to be active for a write to
R/W
H
X
X
L
Description
R
CE
R
X
L
L
X
Right Port
R
HIGH. At least one byte has to be
A
3FFFE
3FFFF
0R–17R
X
X
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INT
H
X
X
L
R