CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 21

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Switching Waveforms
Notes:
44. CE
45. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
46. If t
Left_Port (L_Port) Write to Right_Port (R_Port) Read
CLK
L_PORT
ADDRESS
R/W
L_PORT
DATA
CLK
R_PORT
ADDRESS
R/W
R_PORT
DATA
If t
CCS
CCS
L
L
R
R
0
IN
OUT
= OE = ADS = CNTEN = BE0 – BE7 = LOW; CE
< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t
> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t
t
CKHZ
t
CH2
t
t
CH2
CYC2
t
t
CYC2
CL2
(continued)
t
SW
t
t
SD
SA
t
CL2
D
A
n
n
t
HA
t
CCS
t
SA
1
t
= CNTRST = MRST = CNT/MSK = HIGH.
HW
t
HD
PRELIMINARY
A
n
[44, 45, 46]
t
HA
t
CKLZ
t
DC
t
CD2
CYC2
+ t
Q
CCS
CYC2
CD2
n
) after the rising edge of R_Port's clock.
is violated, indeterminate data will be Read out.
+ t
CD2
) after the rising edge of R_Port's clock.
CYD04S72V
CYD09S72V
CYD18S72V
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