CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet
CYD18S72V
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CYD18S72V Summary of contents
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... JTAG for boundary scan, and asynchronous Master Reset (MRST). The CYD18S72V device have limited features. Please see “Address Counter and Mask Register Operations page 6 for details. Seamless Migration to Next Generation Dual Port Family ...
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... CNTRST L Counter Logic RET L CNTINT WRP L Mailboxes INT L Note: 1. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits. Document #: 38-06069 Rev. *D PRELIMINARY CONFIG Block IO Control Dual Ported Array Arbitration Logic L Address & Counter Logic INT R READY L LowSPD ...
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... Leave this ball unconnected for 128K x 72 and 64K x72 configurations. 8. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO. 9. These balls are not applicable for CYD18S72V device. They need to be tied to VSS. 10. These balls are not applicable for CYD18S72V device. They need connected. ...
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... Master Reset Input. MRST is an asynchronous input signal and affects both ports. A master reset operation is required at power-up. JTAG Reset Input. JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. CYD04S72V CYD09S72V CYD18S72V Description Page ...
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... L L 3FFFF 3FFFE H = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of 1 CYD04S72V CYD09S72V CYD18S72V Description HIGH. At least one byte has Right Port CE A INT R R 0R–17R 3FFFF ...
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... The corresponding bit in the mask register must be a “1” for a counter bit to change. The counter register is incre- mented the least significant bit is unmasked, and masked. If all unmasked bits are “1,” the next increment CYD04S72V CYD09S72V CYD18S72V [14,15 ] Description Page ...
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... The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF. The CYD18S72V has 18 address bits and a maximum address value of 3FFFF. 17. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together. ...
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... Figure 1. Counter, Mask, and Mirror Logic Block Diagram Document #: 38-06069 Rev. *D PRELIMINARY Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic Wrap 17 Bit 0 +1 Wrap 1 Detect CYD04S72V CYD09S72V CYD18S72V Address RAM Decode Array To Readback and Address Decode 17 Wrap To Counter [1] Page ...
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... Boundary Scan Hierarchy for FLEx72 Family Internally, the CYD04S72V and CYD09S72V have two DIEs while CYD18S72V have four DIEs. Each DIE contains all the circuitry required to support boundary scan testing. The circuitry includes the TAP, TAP controller, instruction register, and data registers. The circuity and operation of the DIE boundary scan are described in detail below ...
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... Document #: 38-06069 Rev. *D PRELIMINARY TDO Figure 3. Scan Chain Value 0h Reserved for version number C002h Defines Cypress DIE number for CYD18S72V and CYD09S72V. C001h Defines Cypress DIE number for CYD04S72V 034h Allows unique identification of FLEx72 family device vendor 1 Indicates the presence register Description Captures the Input/Output ring contents ...
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... CYD09S72V CYD04S72V 160 210 CYD09S72V CYD18S72V = Max., OUT Description Test Conditions T = 25° MHz 3.3V DD CYD04S72V CYD09S72V CYD18S72V + 0.5V DD Ambient Temperature V DD 0°C to +70°C 3.3V ± 165 mV –40°C to +85°C 3.3V ± 165 mV -133 -100 Max. Min. Typ Max 2.4 2.4 ...
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... Max. Min. Max. 167 133 6.0 7.5 2.7 3.0 2.7 3.0 2.0 2.0 2.0 2.0 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 CYD04S72V CYD09S72V CYD18S72V 3. 590 Ω 435 Ω 90% 10% < -133 -100 CYD18S72V CYD18S72V Min. Max Min. Max 133 100 7.5 10 3.4 4.5 3.4 4.5 2.0 3.0 2.0 3.0 2.2 2.7 1.0 1.0 2.2 2.7 1.0 1 2.2 2.7 1.0 1.0 2.2 2.7 1.0 1 Page Unit MHz ...
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... Max. Min. 0.6 0.6 NA 2.3 2.5 NA 0.6 0.6 NA 4.0 4 4.0 0 4.4 0 4.0 4.4 4.0 4.4 4.0 4.4 1.0 1.0 1.0 0 4.0 0 4.4 0 1.0 4.0 1.0 4.4 1.0 0.5 6.7 0.5 7.5 0.5 0.5 6.7 0.5 7.5 0.5 0.5 5.0 0.5 5.7 NA 0.5 5.0 0.5 5.7 NA 5.2 6.0 5.7 5.0 5.0 5.0 6.0 6.0 6.0 5.0 5.0 5.0 10.0 10.0 10.0 10.0 CYD04S72V CYD09S72V CYD18S72V -100 CYD18S72V Max Min. Max Unit 5.5 5 5.5 0 5.5 ns 5.0 5 1.0 ns 4.7 0 5.0 ns 4.7 1.0 5.0 ns 7.5 0 7.5 0 8.0 ns 5.0 cycles 8.5 ns 5.0 cycles 10.0 10 Page ...
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... Test Data-In TDI Test Data-Out TDO Document #: 38-06069 Rev. *D PRELIMINARY Description TMSS t TMSH t TDIS t TDIH t TDOX CYD04S72V CYD09S72V CYD18S72V CYD04S72V CYD09S72V CYD18S72V -167/-133/-100 Min. Max. Unit 10 MHz 100 TCYC ...
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... Document #: 38-06069 Rev. *D PRELIMINARY t RSR ACTIVE t CYC2 t CL2 A A n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V IL CYD04S72V CYD09S72V CYD18S72V n n+1 t OHZ t OLZ t OE constantly loads the address on the rising edge of the CLK. IH Page n+2 ...
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... n+1 n+2 n CD2 OPERATION READ CYD04S72V CYD09S72V CYD18S72V CD2 CKHZ CKHZ CKLZ CD2 CKHZ CD2 CKLZ ...
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... PRELIMINARY [31, 34, 36, 37 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE [36] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER CYD04S72V CYD09S72V CYD18S72V A A n+4 n+5 t CD2 READ t HAD t HCN Q n+2 READ WITH COUNTER Page n+4 Q n+3 ...
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... ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D DATA WRITE EXTERNAL ADDRESS Document #: 38-06069 Rev. *D PRELIMINARY [37 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD CYD04S72V CYD09S72V CYD18S72V n+2 n+3 n n+3 n+4 WRITE WITH COUNTER Page ...
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... No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06069 Rev. *D PRELIMINARY 0 t CD2 t CKLZ READ WRITE READ ADDRESS 0 ADDRESS 1 CYD04S72V CYD09S72V CYD18S72V CD2 ...
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... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06069 Rev. *D PRELIMINARY [40, 41, 42, 43 CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CYD04S72V CYD09S72V CYD18S72V A A n+4 n+2 n n+1 n+2 n+3 Page ...
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... CKLZ n t CCS CD2 CNTRST = MRST = CNT/MSK = HIGH. 1 CYD04S72V CYD09S72V CYD18S72V violated, indeterminate data will be Read out. CCS + t ) after the rising edge of R_Port's clock. CYC2 CD2 + t ) after the rising edge of R_Port's clock. CYC2 CD2 Page ...
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... CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 50. The mask register assumed to have the value of 1FFFFh. 51. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06069 Rev. *D PRELIMINARY 1FFFE 1FFFF Last_Loaded t t RCINT SCINT CYD04S72V CYD09S72V CYD18S72V Last_Loaded +1 Page ...
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... Document #: 38-06069 Rev. *D PRELIMINARY n SINT 3FFFF m m+1 [1,14,57,58,59] Inputs CYD04S72V CYD09S72V CYD18S72V A A n+2 n+3 t RINT A A m+3 m+4 Outputs R/W DQ – DQ Operation High-Z Deselected X High-Z Deselected L D Write Read OUT X High-Z Outputs Disabled Page ...
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... Ordering Information 256K × 72 (18Mb) 3.3V Synchronous CYD18S72V Dual-Port SRAM Speed Ordering Code (MHz) 133 CYD18S72V-133BBC 100 CYD18S72V-100BBC CYD18S72V-100BBI 128K × 72 (9Mb) 3.3V Synchronous CYD09S72V Dual-Port SRAM 167 CYD09S72V-167BBC 133 CYD09S72V-133BBC CYD09S72V-133BBI 64K x 72 (4Mb) 3.3 Synchronous CYD04S72V Dual-Port SRAM 167 CYD04S72V-167BBC 133 CYD04S72V-133BBC CYD04S72V-133BBI Document #: 38-06069 Rev ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY 51-85124-*D CYD04S72V CYD09S72V CYD18S72V Page ...
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... Removed FLEX72-E word from the document. Added counter related functions for 4M and 9M. Removed standard JTAG description. Updated block diagram. Updated pinout with FTSEL and one more PORTSTD pins per port. Updated tRSF of CYD18S72V value. CYD04S72V CYD09S72V CYD18S72V ...