CYD18S72V CYPRESS [Cypress Semiconductor], CYD18S72V Datasheet - Page 13

• Manufacturer Part Number: CYD18S72V
• Description: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06069 Rev. *D
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
24. Except INT and CNTINT which are 20pF
25. Except JTAG signal (tr and tf < 10ns max)
26. This parameter is guaranteed by design, but is not production tested
27. Test conditions used are Load 2
Parameter
HRST
SCM
HCM
OE
OLZ
OHZ
CD2
CA2
CM2
DC
CKHZ
CKLZ
SINT
RINT
SCINT
RCINT
CCS
RS
RSS
RSR
RSF
RSCNTINT
Port to Port Delays
Master Reset Timing
[26, 27]
[26, 27]
[26, 27]
[26, 27]
CNTRST Hold Time
CNT/MSK Set-up Time
CNT/MSK Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid
Clock to Counter Address Valid
Clock to Mask Register
Readback Valid
Data Output Hold After Clock
HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset time
Clock to Clock Skew
Master Reset Pulse Width
Master Reset Set-up Time
Master Reset Recovery Time
Master Reset to Outputs
Inactive
Master Reset to Counter
Interrupt Flag Reset Time
Description
Over the Operating Range (continued)
PRELIMINARY
Min.
CYD04S72V
CYD09S72V
0.6
2.3
1.0
1.0
0.5
0.5
5.0
6.0
0.6
0.5
0.5
5.2
5.0
0
0
0
-167
Max.
10.0
10.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
6.7
6.7
5.0
5.0
Min.
CYD04S72V
CYD09S72V
0.6
2.5
0.6
1.0
1.0
0.5
0.5
0.5
0.5
6.0
5.0
6.0
5.0
0
0
0
Max.
10.0
10.0
4.4
4.4
4.4
4.4
4.4
4.4
4.4
7.5
7.5
5.7
5.7
-133
Min.
CYD18S72V
NA
NA
NA
1.0
1.0
0.5
0.5
NA
NA
5.7
5.0
6.0
5.0
0
0
0
Max
10.0
5.5
5.5
5.0
NA
NA
4.7
4.7
7.5
7.5
NA
NA
NA
Min.
CYD18S72V
NA
NA
NA
1.0
1.0
0.5
0.5
NA
NA
8.0
5.0
8.5
5.0
0
0
0
CYD04S72V
CYD09S72V
CYD18S72V
-100
Max
10.0
Page 13 of 26
5.5
5.5
5.2
NA
NA
5.0
5.0
NA
NA
NA
10
10
cycles
cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns