X28HC256D-90 INTERSIL [Intersil Corporation], X28HC256D-90 Datasheet - Page 9

• Manufacturer Part Number: X28HC256D-90
• Description: 5V, Byte Alterable EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Resetting Software Data Protection
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the following six step algorithm will
reset the internal protection circuit. After t
will be in standard operating mode.
FIGURE 9. WRITE SEQUENCE FOR RESETTING SOFTWARE
V
ADDRESS
DATA
WE
CE
CC
WRITE DATA AA
WRITE DATA 20
WRITE DATA AA
WRITE DATA 80
UNPROTECTED
WRITE DATA 55
WRITE DATA 55
TO ADDRESS
TO ADDRESS
TO ADDRESS
TO ADDRESS
TO ADDRESS
TO ADDRESS
AAA
5555
RE-ENTERS
AFTER t
STATE
2AAA
2AAA
5555
5555
5555
5555
9
FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
WC
,
2AAA
55
WC
, the X28HC256
5555
80
X28HC256
5555
AA
Note: Once initiated, the sequence of write operations
should not be interrupted.
SYSTEM CONSIDERATIONS
Because the X28HC256 is frequently used in large memory
arrays, it is provided with a two line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation, and eliminate the
possibility of contention where multiple I/O pins share the
same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read
operation, this assures that all deselected devices are in
their standby mode, and that only the selected device(s)
is/are outputting data on the bus.
Because the X28HC256 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE will cause transient current spikes.
The magnitude of these spikes is dependent on the output
capacitive loading of the l/Os. Therefore, the larger the array
sharing a common bus, the larger the transient spikes. The
voltage peaks associated with the current transients can be
suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended that
a 0.1µF high frequency ceramic capacitor be used between
V
array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between V
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
2AAA
CC
55
and V
SS
5555
20
at each device. Depending on the size of the
t
WC
CC
and V
SS
STANDARD
OPERATING
MODE
for each eight
May 7, 2007
FN8108.2