X28HC256D-90 INTERSIL [Intersil Corporation], X28HC256D-90 Datasheet - Page 5

• Manufacturer Part Number: X28HC256D-90
• Description: 5V, Byte Alterable EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Names
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC256 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 3ms.
Page Write Operation
The page write feature of the X28HC256 allows the entire
memory to be written in typically 0.8 seconds. Page write
allows up to one hundred twenty-eight bytes of data to be
consecutively written to the X28HC256, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A
write cycle to the part during this operation must be the same
as the initial page address.
I/O
SYMBOL
A
0
0
V
V
WE
CE
OE
NC
to A
to I/O
CC
SS
14
7
7
through A
14
5
) for each subsequent valid
Data Input/Output
DESCRIPTION
Address Inputs
Output Enable
Write Enable
Chip Enable
No Connect
Ground
+5V
X28HC256
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 100µs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC256 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
DATA Polling (I/O
The X28HC256 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC256. This eliminates
additional interrupt inputs or external hardware. During the
internal programming cycle, any attempt to read the last byte
written will produce the complement of that data on I/O
write data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
Toggle Bit (I/O
The X28HC256 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle I/O
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
cease, and the device will be accessible for additional read
and write operations.
I/O
DP
FIGURE 1. STATUS BIT ASSIGNMENT
TB
6
)
7
)
5
4
TOGGLE BIT
DATA POLLING
RESERVED
6
7
3
will toggle from HIGH to
will reflect true data.
2
1
May 7, 2007
0
7
FN8108.2
(i.e.,