X28HC256D-90 INTERSIL [Intersil Corporation], X28HC256D-90 Datasheet - Page 8

• Manufacturer Part Number: X28HC256D-90
• Description: 5V, Byte Alterable EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figure 6 and 7 for the sequence. The three-byte sequence
Software Data Protection
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTED STATE
RE-ENTERS DATA
WRITE DATA AA
WRITE DATA A0
LAST ADDRESS
WRITE DATA 55
WRITE DATA XX
TO ADDRESS
TO ADDRESS
TO ADDRESS
WRITE LAST
V
AFTER t
ADDRESS
CC
BYTE TO
TO ANY
WE
CE
2AAA
0V
5555
5555
DATA
ADDRESS
WC
8
BYTE/PAGE
LOAD ENABLED
5555
AAA
OPTIONAL
BYTE/PAGE
LOAD OPERATION
FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE
2AAA
55
X28HC256
5555
A0
≤t
BLC MAX
opens the page write window, enabling the host to write from
one to one hundred twenty-eight bytes of data. Once the
page load cycle has been completed, the device will
automatically be returned to the data protected state.
Regardless of whether the device has previously been
protected or not, once the software data protection algorithm
is used and data has been written, the X28HC256 will
automatically disable further writes unless another command
is issued to cancel it. If no further commands are issued the
X28HC256 will be write protected during power-down and
after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITES
BYTE
AGE
OK
OR
t
WC
WRITE
PROTECTED
(V
CC
)
May 7, 2007
FN8108.2