HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet - Page 20

• Manufacturer Part Number: HYB18H512321BF-08/10
• Description: 512-Mbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

Notes
1. These settings are for debugging purposes only.
2. Default termination values at Power Up.
3. The ODT disable function disables all terminators on the
4. If the user activates bits in the extended mode register in
4.2.1
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to
normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is enabled automatically).
Anytime the DLL is enabled, 1000 cycles must occur before a READ command can be issued.
4.2.2
The WR parameter is programmed using the register bits A4, A5 and A7. This integer parameter defines as a number of clock
cycles the Write Recovery time in a Write with Autoprecharge operation.
The following inequality has to be complied with: WR *
supports WR from 7 to 13. The mid-range bitmap provides WR cycles from 4 to 11.
4.2.3
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and
ZQ / 2 termination values. The termination may also be disabled for testing and other purposes.
4.2.4
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance. When the
auto calibration is used, the output driver impedance is set nominally to ZQ / 6.
If the Output Driver Impendance is changed to 30, 40 or 45 Ohms the user needs to issue 16 AREF commands separated by
t
of
Rev. 1.1, 2007-09
05292007-WAU2-UU95
RFC
t
KO
device.
an optional field, either the optional field is activated (if
consecutively to make the change effective. The user must be aware that the Command bus needs to be stable for a time
after each AREF.
Command
DLL enable
WR
Termination Rtt
Output Driver Impedance
CLK#
CLK
PA
NOP
t
RP
t
CK
EMRS
≥
20
t
WR
5. WR (write recovery time for auto precharge) in clock
, where
A.C.:
Don't Care
option implemented in the device) or no action is taken by
the device (if option not implemented).
cycles is calculated by dividing
to the next integer (WR[cycles] =
mode register must be programmed to this value.
NOP
Any command
t
CK
is the clock cycle time. The high-speed bitmap
t
MRD
Extended Mode Register Set Timing
EMRS: Extended MRS command
PA:
PREALL command
NOP
t
A.C.
WR
t
(in ns) and rounding up
WR
Internet Data Sheet
HYB18H512321BF
[ns] /
512-Mbit GDDR3
FIGURE 9
t
CK
[ns]). The