HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet - Page 16

• Manufacturer Part Number: HYB18H512321BF-08/10
• Description: 512-Mbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

two least significant bits A0 and A1 which are set internally to the fixed value of zero each.Reserved states should not be used,
as unknown operation or incompatibility with future versions may result.
4.1.2
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3).
This device does not support the burst interleave mode.
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
4.1.3
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit
of output data.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident
with clock edge n+m.
The two Mode Register setups support different CAS Latencies in terms of clock cycles. The mid-range-speed Mode Register
supports latencies from 7 to 14. The high-speed Mode Register supports latencies from 10 to 17. The active Mode Register
setup is selected by Bit0 of EMRS2.
4.1.4
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the
first bit of input data.
The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in
Rev. 1.1, 2007-09
05292007-WAU2-UU95
Burst Length
4
8
WL
3-4
5-6-7
A2 A1 A0
— X
0
1
Starting Column Address
Burst type
CAS Latency
Write Latency
X
X
DQ/DM-Receivers
Receivers are always on
Receivers are off and will be switched on by Write command and will be switched off again after
WL+BL
X
X
X
Order of Accesses within a Burst
(Type = sequential)
0-1-2-3
0-1-2-3-4-5-6-7
4-5-6-7-0-1-2-3
16
ON/OFF mode of DQ/DM receivers
Internet Data Sheet
Table
HYB18H512321BF
Burst Definition
512-Mbit GDDR3
TABLE 8
TABLE 9
9.