HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet - Page 13

• Manufacturer Part Number: HYB18H512321BF-08/10
• Description: 512-Mbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

4
4.1
Rev. 1.1, 2007-09
05292007-WAU2-UU95
BA1, BA2
A0-A11
RAS#
CAS#
CLK#
WE#
CKE
CLK
CS#
BA0
Functional Description
Mode Register Set Command (MRS)
COD
Mode Register Set Command
0
0
COD: Code to be loaded into
the register
Don't Care
FIGURE 2
13
The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
up to operate the SGRAM. During a ModeRegister Set
command the address inputs are sampled and stored in the
Mode Register. The Mode Register content can only be set or
changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of
must be met.
The Mode Register Bitmap is supported in two configurations.
The first configuration is intended to support the Mid-Range-
Speed application. The second configuration supports higher
clock cycles for CAS latency and is therefore prepared to
support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
t
MRD