HYB25D256160CC-5 QIMONDA [Qimonda AG], HYB25D256160CC-5 Datasheet - Page 17

no-image

HYB25D256160CC-5

Manufacturer Part Number
HYB25D256160CC-5
Description
256-Mbit Double-Data-Rate SDRAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HYB25D256160CC-5
Manufacturer:
SIEMENS
Quantity:
1
1) CKE is HIGH for all commands shown except Self Refresh.
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A12 provide row address.
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 2.3, 2007-03
03062006-8CCM-VPUW
Name (Function)
Deselect (NOP)
No Operation (NOP)
Active (Select Bank And Activate Row)
Read (Select Bank And Column, And Start Read Burst)
Write (Select Bank And Column, And Start Write Burst)
Burst Terminate
Precharge (Deactivate Row In Bank Or Banks)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
Mode Register Set
Name (Function)
Write Enable
Write Inhibit
Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
Precharge enabled or for write bursts.
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register).
V
REF
must be maintained during Self Refresh operation
17
H
L
L
L
L
L
L
L
CS
L
RAS
X
H
L
H
H
H
L
L
L
X
H
L
L
H
H
L
L
CAS
H
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
WE Address
X
H
H
H
L
L
L
H
L
Truth Table 1b: DM Operation
Truth Table 1a: Commands
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
DM
L
H
Internet Data Sheet
DQs
Valid
X
MNE
NOP
NOP
ACT
Read
Write
BST
PRE
AR/SR
MRS
TABLE 10
TABLE 11
Note
1)
1)
Note
1)2)
1)2)
1)3)
1)4)
1)4)
1)5)
1)6)
1)7)8)
1)9)

Related parts for HYB25D256160CC-5