M58LT256JSB8ZA6 STMICROELECTRONICS [STMicroelectronics], M58LT256JSB8ZA6 Datasheet - Page 84

• Manufacturer Part Number: M58LT256JSB8ZA6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Common Flash Interface
84/106
Table 43.
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables
3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
(P+30)h = 13Ah 02h
(P+31)h = 13Bh 03h
advantageous in a multiplexed device.
M58LT256JST
Offset
Bank and Erase block region 1 information (continued)
Data
(P+30)h = 13Ah
(P+31)h = 13Bh
(P+32)h = 13Ch
(P+33)h = 13Dh
(P+34)h = 13Eh
(P+35)h = 13Fh
(P+36)h = 140h
(P+37)h = 141h
(P+38)h = 142h
(P+39)h = 143h
M58LT256JSB
Offset
Data
0Eh Bank region 1 Erase Block type 2 information
02h
03h
00h
00h
02h
64h
00h
02h
03h
Bank region 1 (Erase Block type 1): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
Bank region 1 (Erase Block type 1): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
Bits 0-15: n+1 = number of identical-sized
erase blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
Bank region 1 (Erase Block type 2)
Minimum block erase cycles × 1000
Bank regions 1 (Erase Block Type 2): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
Bank region 1 (Erase Block Type 2): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
29
to 34.
M58LT256JST, M58LT256JSB
Description