M48Z35-70MH1TR STMICROELECTRONICS [STMicroelectronics], M48Z35-70MH1TR Datasheet - Page 8

• Manufacturer Part Number: M48Z35-70MH1TR
• Description: 256 Kbit (32 Kbit x 8) ZEROPOWER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48Z35, M48Z35Y
READ Mode
The M48Z35/Y is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
Figure 8. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
8/20
A0-A14
E
G
DQ0-DQ7
AVQV
) after the last
tAVQV
tELQX
tELQV
tGLQX
tGLQV
tAVAV
VALID
available after the latter of the Chip Enable Access
time (t
(t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
Address Access.
GLQV
AXQX
).
ELQV
AVQV
) but will go indeterminate until the next
VALID
) or Output Enable Access time
, the data lines will be driven to an
tGHQZ
AVQV
. If the Address In-
tAXQX
tEHQZ
AI00925