M48Z35-70MH1TR STMICROELECTRONICS [STMicroelectronics], M48Z35-70MH1TR Datasheet - Page 10

• Manufacturer Part Number: M48Z35-70MH1TR
• Description: 256 Kbit (32 Kbit x 8) ZEROPOWER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48Z35, M48Z35Y
WRITE Mode
The M48Z35/Y is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of
W or E. The addresses must be held valid through-
out the cycle. E or W must return high for a mini-
mum of t
WRITE Enable prior to the initiation of another
Figure 9. WRITE Enable Controlled, WRITE AC Waveforms
Figure 10. Chip Enable Controlled, WRITE AC Waveforms
10/20
EHAX
A0-A14
E
W
DQ0-DQ7
A0-A14
E
W
DQ0-DQ7
from Chip Enable or t
tAVEL
tAVEL
tAVWL
tAVWL
WHAX
tWLQZ
from
tAVWH
tAVEH
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
READ or WRITE cycle. Data-in must be valid t
VWH
t
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
WHDX
prior to the end of WRITE and remain valid for
tDVEH
tDVWH
afterward. G should be kept high during
DATA INPUT
DATA INPUT
tWHDX
tEHDX
tWHQX
tEHAX
tWHAX
AI00926
AI00927
WLQZ
D-