DM9620 DAVICOM [Davicom Semiconductor, Inc.], DM9620 Datasheet - Page 21

• Manufacturer Part Number: DM9620
• Description: USB2.0 to 10/100M Fast Ethernet Controller
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

4.9 RX/TX Flow Control Register ( 0AH )
4.10 EEPROM & PHY Control Register ( 0BH )
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
EE_TYPE
NO_EEP
ERPRW
RXPCS
ERPRR
TXPEN
BKPM
EPOS
Name
BKPA
RXPS
Name
REEP
TXPF
FLCE
TXP0
WEP
PHS0,RW/C
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RO
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
Default
Default
P0,RO
P0,RO
Force to TX Pause Packet with Time 0000H,:
This bit will be automatically cleared after pause packet transmission
completion.
Set to TX pause packet with time = 0000H
Force to TX Pause Packet with Time FFFFH:
This bit will be automatically cleared after pause packet transmission
completion.
Set to TX pause packet with time = FFFFH.
TX Pause Packet Enable
Enable the pause packet for high/low water threshold of register 09H in
Back Pressure Packet Mode Enable:
Generate a jam pattern when any packet coming and RX SRAM over BPHW
of register 8H in half-duplex mode.
BPHW of register 8H in half-duplex mode.
RX Pause Packet Status:
RX Pause Packet Current Status:
Flow Control Enable
When set, it enable the flow control mode(i.e. can to disable TX function).
EEPROM Absent
EEPROM type
0: 93C46
1: 93C56/66
Reload EEPROM.
Write EEPROM enable
EEPROM or PHY Operation Select
When reset, select EEPROM;
when set, select PHY.
EEPROM Read or PHY Register Read Command.
Write “1” to start EEPROM or PHY read operation.
This bit will be cleared after the completion of read operation.
EEPROM Write or PHY Register Write Command.
Write “1” to start EEPROM or PHY write operation.
This bit will be cleared after the completion of write operation
Back Pressure DA Mode.
This bit can be cleared by write “1” to this bit or cleared automatically after
When set, it indicated that the pause timer is not down count to “0” yet.
When set, it indicates the EEPROM 93C46 or 93C56/66 is not detected.
Generate a jam pattern when a packet’s DA match and RX SRAM over
The written ability of EEPROM is enabled.
full-duplex mode.
This bit latched the RX pause packet in full-duplex mode.
read if register 0H bit 5 is “0”.
When set, the EEPROM is re-loaded.
Driver needs to clear it after operation complete.
Description
Description
USB2.0 to Fast Ethernet Controller
DM9620
21