CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 26

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

26
ISCLK
ILRCK
SDIN
SDA/CDOU
T
SCL/CCLK
AD0/CS
AD1/CDIN
AD2
RXP
INT
TCBL
U
NC1
NC2
NC3
NC4
NC5
13
12
14
28
27
19
15
20
10
16
17
18
11
1
2
3
4
Serial Audio Bit Clock ( Input / Output ) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Input Left/Right Clock ( Input / Output ) - Word rate clock for the audio data on
the SDIN pin.
Serial Audio Data Port ( Input ) - Audio data serial input pin.
Serial Control Data I/O (I²C Mode) / Data Out (SPI) ( Input/Output ) - In I²C Mode, SDA is the
control I/O data line. SDA is open drain and requires an external pull-up resistor to VL+. In
SPI mode, CDOUT is the output data from the control port interface on the CS8405A
Control Port Clock ( Input ) - Serial control interface clock and is used to clock control data
bits into and out of the CS8405A. In I²C mode, SCL requires an external pull-up resistor to
VL+.
Address Bit 0 (I²C Mode) / Control Port Chip Select (SPI) ( Input) - A falling edge on this pin
puts the CS8405A into SPI control port mode. With no falling edge, the CS8405A defaults to
I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the con-
trol port interface on the CS8405A
Address Bit 1 (I²C Mode) / Serial Control Data in (SPI) ( Input ) - In I²C mode, AD1 is a chip
address pin. In SPI mode, CDIN is the input data line for the control port interface.
Address Bit 2 (I²C Mode) ( Input ) - Determines the AD2 address bit for the control port in I²C
mode, and should be connected to DGND or VL+. If SPI mode is used, the AD2 pin should be
connected to DGND.
Auxiliary AES3 Receiver Port ( Input ) - Input for an alternate, already bi-phase encoded,
audio data source.
Interrupt ( Output ) - Indicates key events during the operation of the CS8405A. All bits affect-
ing INT may be unmasked through bits in the control registers. Indication of the condition(s)
that initiated an interrupt are readable in the control registers. The polarity of the INT output,
as well as selection of a standard or open drain output, is set through a control register. Once
set true, the INT pin goes false only after the interrupt status registers have been read and the
interrupt status bits have returned to zero.
Transmit Channel Status Block Start ( Input / Output ) - When operated as output, TCBL is
high during the first sub-frame of a transmitted channel status block, and low at all other
times. When operated as input, driving TCBL high for at least three OMCK clocks will cause
the next transmitted sub-frame to be the start of a channel status block.
User Data ( Input / Output ) - May optionally be used to input User data for transmission by the
AES3 transmitter, see Figure 7 for timing information. Alternatively, the U pin may be set to
output, which also selects the internal buffer as the source of transmitted U data. If not driven,
a 47 kW pull-down resistor is recommended for the U pin, because the default state of the UD
direction bit sets the U pin as an input. The pull-down resistor ensures that the transmitted
user data will be zero. If the U pin is always set to be an output, thereby causing the U bit
manager to be the source of the U data, then the resistor is not necessary. The U pin should
not be tied directly to ground, in case it is programmed to be an output, and subsequently
tries to output a logic high. This situation may affect the long term reliability of the device. If
the U pin is driven by a logic level output, then a 100 W series resistor is recommended.
No Connect - These pins should not be connected to any signals or PCB trace. They may be
driven high and/or low by the CS8405A.
CS8405A
DS469F2