CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 17

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

7.
7.1
Note:
DS469F2
(HEX)
14-1F Reserved
20-37 C or U Data Buffer
0F-11 Reserved
Addr
0C
0D
0A
0B
0E
7F
00
01
02
03
04
05
06
07
08
09
12
13
INCR
CONTROL PORT REGISTER SUMMARY
7
Reserved
Control 1
Control 2
Data Flow Control
Clock Source Control
Serial Input Format
Reserved
Interrupt 1 Status
Interrupt 2 Status
Interrupt 1 Mask
Interrupt 1 Mode (MSB) TSLIP1
Interrupt 1 Mode (LSB)
Interrupt 2 Mask
Interrupt 2 Mode (MSB)
Interrupt 2 Mode (LSB)
CS Data Buffer Control
U Data Buffer Control
ID and Version
MEMORY ADDRESS POINTER (MAP)
Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8405A.
INCR - Auto Increment Address Control Bit
MAP6:MAP0 - Register Address
Default = ‘0’
0 - Disable
1 - Enable
Function
MAP6
6
TSLIPM
TSLIP0
MAP5
TSLIP
SIMS
ID3
5
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 1. Control Register Map Summary
TXOFF AESBP
VSET
RUN
SISF
ID2
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAP4
4
SIRES1
BSEL
CLK1
ID1
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAP3
MUTEAES
SIRES0
3
CLK0
ID0
UD
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIJUST
UBM1
VER3
MAP2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
EFTUM
EFTU1
EFTU0
SIDEL
EFTCI
UBM0
EFTU
VER2
INT1
MMT
2
0
0
0
0
0
0
0
0
0
0
MAP1
1
MMCST
SISPOL SILRPOL
EFTCM
EFTC1
EFTC0
EFTC
VER1
INT0
CAM
1
0
0
0
0
0
0
0
0
0
0
0
CS8405A
MAP0
MMTLR
TCBLD
EFTUI
VER0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17