CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 19

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

8.3
8.4
DS469F2
7
0
7
0
Data Flow Control (03h)
Clock Source Control (04h)
MMTLR - Channel Selection for AES Transmitter mono mode
TXOFF - AES3 Transmitter Output Driver Control
AESBP - AES3 bypass mode selection
RUN - Controls the internal clocks, allowing the CS8405A to be placed in a “powered down” low
current consumption, state.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector.
If these bits are changed during normal operation, then always stop the CS8405A first (RUN = 0),
write the new value, then start the CS8405A (RUN = 1).
Default = ‘0’
0 - Use left channel input data for consecutive subframe outputs
1- Use right channel input data for consecutive subframe outputs
The Data Flow Control register configures the flow of audio data. The output data should be muted
prior to changing bits in this register to avoid transients.
Default = ‘0
0 - AES3 transmitter output pin drivers normal operation
1 - AES3 transmitter output pin drivers drive to 0 V.
Default = ‘0’
0 - Normal operation
1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL
threshold digital input. The OMCK clock must be present for the bypass mode to work.
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control
register, various Receiver/Transmitter/Transceiver modes may be selected.
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
1 - Normal part operation. This bit must be set to 1 to allow the CS8405A
Default = ‘00’
00 - OMCK frequency is 256*Fs
01 - OMCK frequency is 384*Fs
10 - OMCK frequency is 512*Fs
11 - Reserved
control port registers are operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
TXOFF
RUN
6
6
AESBP
CLK1
5
5
CLK0
4
4
0
3
0
3
0
2
0
2
0
1
1
0
0
CS8405A
0
0
0
0
19