CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 21

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

8.6
8.7
8.8
DS469F2
TSLIPM
TSLIP
7
7
0
7
Interrupt 1 Status (07h) (Read Only)
Interrupt 2 Status (08h) (Read Only)
Interrupt 1 Mask (09h)
TSLIP - AES3 transmitter source data slip interrupt
EFTC - E to F C-buffer transfer interrupt.
EFTU - E to F U-buffer transfer interrupt. (Block Mode only)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once
since the register was last read. A ”0” means the associated interrupt condition has NOT occurred
since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode
is set to level and the interrupt source is still true. Status bits that are masked off in the associated
mask register will always be “0” in this register. This register defaults to 00h.
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source,
this bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit
will go high on receipt of a new TCBL signal.
The source for this bit is true during the E to F buffer transfer in the C bit buffer management process.
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once
since the register was last read. A ”0” means the associated interrupt condition has NOT occurred
since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode
is set to level and the interrupt source is still true. Status bits that are masked off in the associated
mask register will always be “0” in this register. This register defaults to 00h.
The source of this bit is true during the E to F buffer transfer in the U bit buffer management process.
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error
is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit
is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status
register. The bit positions align with the corresponding bits in Interrupt 1 register. This register defaults
to 00h.
6
6
6
0
0
0
5
0
5
0
5
0
4
4
4
0
0
0
3
0
3
0
3
0
EFTU
2
0
2
2
0
EFTCM
EFTC
1
1
1
0
CS8405A
0
0
0
0
0
0
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