CS18LV20483ACC-55 ETC1 [List of Unclassifed Manufacturers], CS18LV20483ACC-55 Datasheet - Page 4

• Manufacturer Part Number: CS18LV20483ACC-55
• Description: High Speec Super Low Power SRAM
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

PIN DESCRIPTIONS
TRUTH TABLE
Disabled
Standby
Output
Name
MODE
/CE1, CE2
DQ0~DQ7
Write
Read
Chiplus reserves the right to change product or specification without notice.
A0 – A17
Gnd
/WE
Vcc
/OE
NC
Power
Power
Type
/CE1
Input
Input
Input
Input
I/O
H
X
L
L
L
256K-Word By 8 Bit
Address inputs for selecting one of the 262,144 x 8 bit words in the RAM
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
active when data read from or write to the device. If either chip enable is
not active, the device is deselected and in a standby power down mode.
The DQ pins will be in high impedance state when the device is
deselected.
The Write enable input is active LOW. It controls read and write
operations. With the chip selected, when /WE is HIGH and /OE is LOW,
output data will be present on the DQ pins, when /WE is LOW, the data
present on the DQ pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active
while the chip is selected and the write enable is inactive, data will be
present on the DQ pins and they will be enabled. The DQ pins will be in
the high impedance state when /OE is inactive.
These 8 bi-directional ports are used to read data from or write data into
the RAM.
Power Supply
Ground
No connection
CE2
High Speed Super Low Power SRAM
H
H
H
X
L
/WE
X
X
H
H
L
4
/OE
H
X
X
L
L
Function
DQ0~7
High Z
High Z
D
D
OUT
IN
CS18LV20483
Vcc Current
I
CCSB
I
I
I
, I
CC
CC
CC
CCSB1
Rev. 1.0