CS18LV20483ACC-55 ETC1 [List of Unclassifed Manufacturers], CS18LV20483ACC-55 Datasheet - Page 12

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CS18LV20483ACC-55

Manufacturer Part Number
CS18LV20483ACC-55
Description
High Speec Super Low Power SRAM
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
NOTES:
1. A write occurs during the overlap(t
2. t
3. t
4. t
begins when /CE1 goes low, CE2 going high and /WE goes low. A write ends at the
earliest transition when /CE1 goes high , CE2 goes high an /WE goes high. The t
measured from the beginning of the write to the end of write.
write ends as /CE1 or /WE going high or CE2 going low.
CW
AS
WR
ORDER INFORMATION
Chiplus reserves the right to change product or specification without notice.
is measured from the address valid to the beginning of write.
is measured from the /CE1 going low or CE2 going low to end of write.
is measured from the end or write to the address change. T
256K-Word By 8 Bit
High Speed Super Low Power SRAM
WP
12
) of low /CE1, a high CE2 and low /WE. A write
WR
CS18LV20483
applied in case a
Rev. 1.0
WP
is

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