CS18LV20483ACC-55 ETC1 [List of Unclassifed Manufacturers], CS18LV20483ACC-55 Datasheet
CS18LV20483ACC-55
Related parts for CS18LV20483ACC-55
CS18LV20483ACC-55 Summary of contents
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By 8 Bit Revision History Rev. No. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM History Initial issue 1 CS18LV20483 Issue Date Remark Jan.26,2005 Rev. 1.0 ...
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By 8 Bit GENERAL DESCRIPTION The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V ...
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High Speed Super Low Power SRAM 256K-Word By 8 Bit PIN CONFIGURATIONS Chiplus reserves the right to change product or specification without notice. FUNCTIONAL BLOCK DIAGRAM 3 CS18LV20483 Rev. 1.0 ...
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High Speed Super Low Power SRAM 256K-Word By 8 Bit PIN DESCRIPTIONS Type Name A0 – A17 Input Address inputs for selecting one of the 262,144 x 8 bit words in the RAM /CE1 is active LOW and CE2 is ...
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By 8 Bit ABSOLUTE MAXIMUM RATINGS (1) Symbol V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current OUT 1. Stresses greater than those ...
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By 8 Bit DC ELECTRICAL CHARACTERISTICS Parameter Parameter Name V Guaranteed Input Low IL (2) Voltage V Guaranteed Input High IH (2) Voltage I Input Leakage Current Output Leakage OL Current V Output Low Voltage OL ...
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By 8 Bit LOW Vcc DATA RETENTION WAVEFORM 1 ( /CE1 Controlled ) LOW Vcc DATA RETENTION WAVEFORM 2 ( CE2 Controlled ) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference ...
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By 8 Bit AC TEST LOADS AND WAVEFORMS FIGURE 1A AC ELECTRICAL CHARACTERISTICS < READ CYCLE > JEDEC Parameter Parameter Name Name Read Cycle Time t t AVAX Address Access Time AVQV AA Chip Select Access ...
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By 8 Bit SWITCHING WAVEFORMS (READ CYCLE) NOTES and t are defined as the outputs achieve the open circuit conditions and are not HZ OHZ referenced to output voltage levels any given temperature and voltage ...
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By 8 Bit AC ELECTRICAL CHARACTERISTICS ( < WRITE CYCLE > JEDEC Parameter Parameter Name Name t t Write Cycle Time AVAX Chip Select to End of Write E1LWH CW Address Setup Time t t AVWL ...
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High Speed Super Low Power SRAM 256K-Word By 8 Bit SWITCHING WAVEFORMS (WRITE CYCLE) Chiplus reserves the right to change product or specification without notice. 11 CS18LV20483 Rev. 1.0 ...
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By 8 Bit NOTES write occurs during the overlap(t begins when /CE1 goes low, CE2 going high and /WE goes low. A write ends at the earliest transition when /CE1 goes high , CE2 goes high an ...
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