FAN3268_11 FAIRCHILD [Fairchild Semiconductor], FAN3268_11 Datasheet - Page 11

• Manufacturer Part Number: FAN3268_11
• Description: 2A Low-Voltage PMOS-NMOS Bridge Driver
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
Applications Information
Input Thresholds
The FAN3268 driver has TTL input thresholds and
provides buffer and level translation functions from logic
inputs. The input thresholds meet industry-standard
TTL-logic thresholds, independent of the V
and there is a hysteresis voltage of approximately 0.4V.
These levels permit the inputs to be driven from a range
of input logic signal levels for which a voltage over 2V is
considered logic high. The driving signal for the TTL
inputs should have fast rising and falling edges with a
slew rate of 6V/µs or faster, so a rise time from 0 to 3.3V
should be 550ns or less. With reduced slew rate, circuit
noise could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the driver input, causing
erratic operation.
Static Supply Current
In the I
(see Figure 6), the curve is produced with all inputs /
enables floating (OUT is low) and indicates the lowest
static I
states, additional current flows through the 100k
resistors on the inputs and outputs shown in the block
diagram (see Figure 3). In these cases, the actual static
I
this additional current.
MillerDrive™ Gate Drive Technology
FAN3268 gate drivers incorporate the MillerDrive™
architecture shown in 0. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between one and two
thirds V
high or low rail.
The purpose of the MillerDrive™ architecture is to speed
up switching by providing high current during the Miller
plateau region when the gate-drain capacitance of the
MOSFET is being charged or discharged as part of the
turn-on / turn-off process.
For applications with zero voltage switching during the
MOSFET turn-on or turn-off interval, the driver supplies
high peak current for fast switching even though the
Miller plateau is not present. This situation often occurs
in synchronous rectifier applications because the body
diode is generally conducting before the MOSFET is
switched on.
The output pin slew rate is determined by V
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall time
at the MOSFET gate is needed.
DD
current is the value obtained from the curves plus
DD
DD
DD
current for the tested configuration. For other
and the MOS devices pull the output to the
(static) typical performance characteristics
DD
DD
voltage,
voltage
11
Under-Voltage Lockout
Internal circuitry provides an under-voltage lockout
function that prevents the output switching devices from
operating if the V
operating level. When V
operational level, internal 100k resistors bias the non-
inverting output low and the inverting output to V
keep the external MOSFETs off during startup intervals
when logic control signals may not be present. After the
part is active, the supply voltage must drop 0.2V before
the part shuts down. This hysteresis helps prevent
chatter when low V
the power switching.
V
To enable this IC to turn a device on quickly, a local
high-frequency bypass capacitor C
ESL should be connected between the VDD and GND
pins with minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10µF to 47µF
commonly found on driver and controller bias circuits.
A typical criterion for choosing the value of C
keep the ripple voltage on the V
often achieved with a value ≥20 times the equivalent
load capacitance C
Ceramic capacitors of 0.1µF to 1µF or larger are
common choices, as are dielectrics, such as X5R and
X7R, with good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
C
may be split into two capacitors. One should be a larger
value, based on equivalent load capacitance, and the
other a smaller value, such as 1-10nF mounted closest
to the VDD and GND pins to carry the higher frequency
components of the current pulses. The bypass capacitor
must provide the pulsed current from both of the driver
channels
simultaneously, the combined peak current sourced
from the C
channel is switching.
BYP
DD
Figure 27. MillerDrive™ Output Architecture
Bypass Capacitor Guidelines
may be increased to 50-100 times the C
BYP
and,
would be twice as large as when a single
DD
if
DD
EQV
supply voltages have noise from
, defined here as Q
the
supply voltage is below the
DD
is rising, but below the 3.9V
drivers
DD
supply to ≤5%. This is
BYP
with low ESR and
are
www.fairchildsemi.com
EQV
switching
GATE
BYP
or C
DD
/V
is to
BYP
DD
to
.