STA559BWQS13TR STMICROELECTRONICS [STMicroelectronics], STA559BWQS13TR Datasheet - Page 59

• Manufacturer Part Number: STA559BWQS13TR
• Description: 5-V, 2-A, 2.1-channel high-efficiency digital audio system with QSound QHD
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STA559BWQS
6
6.1
6.2
Application
Application scheme for power supplies
Figure 33
care has to be given to the layout of the PCB, especially the power supplies. The 3.3-Ω
resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the
device. This helps to prevent unwanted oscillation on the digital portion of the device due to
inductive tracks of the PCB. This same rule also applies to all the decoupling capacitors in
order to limit any kind of spikes on the supplies.
Figure 33. Application schematic
PLL filter schematic
It is recommended to use the below schematic and values in
loop filter. In order to achieve the best performance from the device in general applications
the filter ground (PLL_GND) must be connected as close as possible to the device pin
PLL_GND. Concerning the component values, please take into account that the greater is
the filter bandwidth, the less is the lock time but the higher is the PLL output jitter.
Figure 34. PLL application schematic
1000uF 35V
1000uF 35V
1000uF 35V
1000uF 35V
1uF 35V
1uF 35V
100nF
100nF
1uF 35V
1uF 35V
100nF
100nF
below shows a circuit diagram of a typical application for STA559BWQS.Particular
VCC
VCC
VCC
VCC
DDX3B
DDX3B
DDX3A
DDX3A
OUT2B
OUT2B
OUT2A
OUT2A
OUT2A
OUT2A
OUT1B
OUT1B
OUT1B
OUT1B
OUT1A
OUT1A
OUT1A
OUT1A
100nF
100nF
100nF
100nF
100nF
100nF
GND_DIG
GND_DIG
FILTER_PLL
FILTER_PLL
FILTER_PLL
FILTER_PLL
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
17
17
17
17
18
18
18
18
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
BEAD
BEAD
BEAD
GND_SUB
GND_SUB
GND_SUB
GND_SUB
SA
SA
SA
SA
TEST_MODE
TEST_MODE
TEST_MODE
TEST_MODE
VSS
VSS
VSS
VSS
VCC_REG
VCC_REG
VCC_REG
VCC_REG
OUT2B
OUT2B
OUT2B
OUT2B
GND2
GND2
GND2
GND2
VCC2
VCC2
VCC2
VCC2
OUT2A
OUT2A
OUT2A
OUT2A
OUT1B
OUT1B
OUT1B
OUT1B
VCC1
VCC1
VCC1
VCC1
GND1
GND1
GND1
GND1
OUT1A
OUT1A
OUT1A
OUT1A
GND_REG
GND_REG
GND_REG
GND_REG
VDD
VDD
VDD
VDD
GND
CONFIG
CONFIG
CONFIG
CONFIG
DDX3B
DDX3B
DDX3B
DDX3B
DDX3A
DDX3A
DDX3A
DDX3A
2K2
2K2
2K2
2K2
4.7nF
4.7nF
4.7nF
4.7nF
FILTER_PLL
FILTER_PLL
FILTER_PLL
FILTER_PLL
TWARN/4A
TWARN/4A
TWARN/4A
TWARN/4A
PLL_GND
PLL_GND
PLL_GND
PLL_GND
GND_DIG
GND_DIG
GND_DIG
GND_DIG
VDD_PLL
VDD_PLL
VDD_PLL
VDD_PLL
GND_DIG
GND_DIG
GND_DIG
GND_DIG
VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG
INT_LINE
INT_LINE
INT_LINE
INT_LINE
VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG
EAPD/4B
EAPD/4B
EAPD/4B
EAPD/4B
PWRDN
PWRDN
PWRDN
PWRDN
RESET
RESET
RESET
RESET
LRCKI
LRCKI
LRCKI
LRCKI
BICKI
BICKI
BICKI
BICKI
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDI
SDI
SDI
SDI
XTI
XTI
XTI
XTI
100pF
100pF
100pF
100pF
36
36
36
36
35
35
35
35
34
34
34
34
33
33
33
33
32
32
32
32
31
31
31
31
30
30
30
30
29
29
29
29
28
28
28
28
27
27
27
27
26
26
26
26
25
25
25
25
24
24
24
24
23
23
23
23
22
22
22
22
21
21
21
21
20
20
20
20
19
19
19
19
3R3
3R3
PLL_GND
PLL_GND
PLL_FILT
PLL_FILT
PLL_FILT
PLL_FILT
TW
TW
EAPD
EAPD
3R3
3R3
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
INTL
INTL
Figure 34
DATA
DATA
DATA
DATA
LRCKI
LRCKI
BICKI
BICKI
XTI
XTI
680pF
680pF
680pF
680pF
100nF
100nF
100nF
100nF
PWDN
PWDN
GND_DIG
GND_DIG
100nF
100nF
100nF
100nF
BEAD
BEAD
BEAD
3V3
3V3
10K
10K
10K
10K
below for the PLL
Component leads
must be kept as
short as possible
GND_DIG
GND_DIG
1nF
1nF
1nF
1nF
PLL_GND
PLL_GND
GND_DIG
GND_DIG
BEAD
BEAD
RESET
RESET
RESET
RESET
3V3
3V3
Application
3V3
3V3
3V3
3V3
RESET
RESET
RESET
RESET
GND_DIG
GND_DIG
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