STA559BWQS13TR STMICROELECTRONICS [STMicroelectronics], STA559BWQS13TR Datasheet - Page 23

• Manufacturer Part Number: STA559BWQS13TR
• Description: 5-V, 2-A, 2.1-channel high-efficiency digital audio system with QSound QHD
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STA559BWQS
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
I
The STA559BWQS supports the I
to slave) and the output port SDA_OUT (slave to master). This protocol defines any device
that sends data on to the bus as a transmitter and any device that reads the data as a
receiver. The device that controls the data transfer is known as the master and the other as
the slave. The master always starts the transfer and provides the serial clock for
synchronization. STA559BWQS is always a slave device in all of its communications. It
supports up to 400 kb/s rate (fast-mode bit rate). STA559BWQS I
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA559BWQS and the bus master.
Data input
During the data input the STA559BWQS samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of
the clock and the data can change only when the SCL line is low.
Device addressing
To start communication between the master and the STA559BWQS, the master must initiate
with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first)
corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I
definition. In the STA559BWQS the I
the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0
for write mode. After a START condition the STA559BWQS identifies on the bus the device
address and if a match is found, it acknowledges the identification on SDA bus during the
9th bit time. The byte following the device identification byte is the internal space address.
2
C bus specification
2
C protocol via the input ports SCL and SDA_IN (master
2
C interface has two device addresses depending on
2
C is a slave only interface.
I
2
C bus specification
2
C bus
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