STA559BWQS13TR STMICROELECTRONICS [STMicroelectronics], STA559BWQS13TR Datasheet
STA559BWQS13TR
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STA559BWQS13TR Summary of contents
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... Preset night-time listening mode ! Individual channel and master soft and hard mute ! Independent channel volume and DSP bypass Table 1. Order codes Part number STA559BWQS 0 to 150 STA559BWQS13TR 0 to 150 March 2008 ! Automatic zero-detect mute ! Automatic invalid input detect mute ! 2-channel I ! ...
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Contents Contents 1 Description and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 ...
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STA559BWQS 4.4.4 4.4.5 4.4.6 5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 5.5.7 5.5.8 5.6 Configuration register F (addr 0x05 5.6.1 5.6.2 ...
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STA559BWQS 5.12.1 5.12.2 5.12.3 5.12.4 5.12.5 5.12.6 5.12.7 5.12.8 5.12.9 5.12.10 Coefficient a1 data register bits 7.. ...
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Contents 10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 64 11 Revision history . . . . . . . . ...
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STA559BWQS Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 54. Channel volume as a function of CxV[7: ...
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STA559BWQS Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description and block diagram 1 Description and block diagram 1.1 Description The STA559BWQS is an integration of digital audio processing, digital amplifier control, ® DDX power-output stage and QSound QHD single-chip DDX solution with high-quality, high-efficiency and all digital amplification. ...
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STA559BWQS 1.3 Block diagram Figure 1. Block diagram interface DSP (Equalization, Tone, Volume, Bass) PLL Digital (DSP Protection current/thermal Power control DDX Regulators Description and block diagram Channel 1A Channel 1B Logic Channel 2A ...
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Connections diagram and pins description 2 Connections diagram and pins description 2.1 Connections diagram Figure 2. Pin connection PowerSSO-36 (top view) GND_SUB TEST_MODE VCC_REG GND_REG OUT3B/DDX3B OUT3A/DDX3A 2.2 Pins description Table 2. Pin description Pin ...
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STA559BWQS Table 2. Pin description (continued) Pin Connections diagram and pins description Type ...
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Connections diagram and pins description 2.3 Thermal data Table 3. Thermal data Symbol R Thermal resistance junction-ambient PowerSSO-36 th j-amb T Thermal shut-down junction temperature th-sdj T Thermal warning temperature th-w T Thermal shut-down hysteresis temperature th-sdh 1. See Chapter ...
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STA559BWQS 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V Power supply voltage (VCC1, VCC2) cc Vdd Logic supply T Operating junction temperature op T Storage temperature stg Note: Stresses beyond those listed under “Absolute ...
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Electrical specifications 3.3 Electrical specifications - digital section Table 6. Electrical specifications - digital section Symbol Parameter I Low level input current without pull device High level input current without pull device ih V ...
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STA559BWQS Table 7. Electrical specifications - power Section (continued) Symbol Parameter Ilim Overcurrent limit Isc Short circuit protection Under voltage protection UVL threshold t Output minimum pulse width min Output power BTL Output power SE Output power BTL Po Output ...
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Electrical specifications 3.5 Testing 3.5.1 Functional pin status Table 8. Functional pin status Pin name Pin # PWRDN 23 PWRDN 23 TWARN 20 TWARN 20 EAPD 19 EAPD 19 Figure 3. Test circuit 1 Duty cycle = 50% Figure 4. ...
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STA559BWQS 3.6 Electrical characteristics curves Figure 5. Output power vs supply voltage ( Ω) Po(W) 3 2.5 Rload = 2Ώ 1KHz 2 S.E. 1.5 1 THD=1% 500m 0 +4.5 +4.6 +4.7 +4.8 +4.9 +5 +5.1 +5.2 ...
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Electrical specifications Figure 11. Output power vs. supply voltage ( Ω) Po(W) 3 2.7 2.4 2.1 Rload = 8Ώ 1 1KHz 1.5 SE 1.2 0.9 0.6 0.3 0 +4.5 +5 +5.5 +6 +6.5 +7 +7.5 Vcc(V) ...
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STA559BWQS Figure 17. PSSR +10 dBr +0 -10 Vcc = 5V - -30 -40 -50 -60 -70 -80 -90 -100 Frequency Hz Figure 19. Channel separation stereo S. Ω) mode ...
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Electrical specifications Figure 23. FFT 0 dBFS stereo S.E. mode (R 4 Ω) dBr A +10 +0 Stereo S.E. Mode -10 -20 Vcc=5V, Rl=4Ώ - 1KHz -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20 50 ...
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STA559BWQS bus specification The STA559BWQS supports the I to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device ...
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I C bus specification 4.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA559BWQS acknowledges this and the writes for the byte of internal address. After ...
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STA559BWQS 4.4.5 Write mode sequence Figure 27. Write mode sequence BYTE DEV-ADDR WRITE START MULTIBYTE DEV-ADDR WRITE START 4.4.6 Read mode sequence Figure 28. Read mode sequence CURRENT DEV-ADDR ADDRESS READ START RANDOM DEV-ADDR ADDRESS READ START SEQUENTIAL DEV-ADDR CURRENT ...
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Register description 5 Register description Table 9. Register summary Addr Name D7 0x00 ConfA FDRB 0x01 ConfB C2IM 0x02 ConfC OCRB 0x03 ConfD MME 0x04 ConfE SVE 0x05 ConfF EAPD 0x06 Mute/LOC LOC1 0x07 Mvol MV7 0x08 C1Vol C1V7 0x09 ...
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STA559BWQS Table 9. Register summary (continued) Addr Name D7 0x20 A2cf1 C4B23 0x21 A2cf2 C4B15 0x22 A2cf3 C4B7 0x23 B0cf1 C5B23 0x24 B0cf2 C5B15 0x25 B0cf3 C5B7 0x26 Cfud 0x27 MPCC1 MPCC15 MPCC14 0x28 MPCC2 MPCC7 0x29 DCC1 DCC15 0x2A ...
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Register description The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency The relationship between the input clock and the input sample rate is determined by both the MCSx ...
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STA559BWQS 5.1.3 Thermal warning recovery bypass Table 14. Thermal warning recovery bypass Bit thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery will determine if the -3 dB output limit is removed ...
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Register description 5.2 Configuration register B (addr 0x01 C2IM C1IM 1 0 5.2.1 Serial audio input interface format Table 17. Serial audio input interface format Bit 5.2.2 Serial data ...
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STA559BWQS Table 19. Support serial audio input formats for MSB-First (SAIFB = 0) (continued) BICKI Table 20. Supported serial audio input formats for LSB-First (SAIFB = 1) BICKI SAI [3:0] SAIFB 2 ...
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Register description Table 20. Supported serial audio input formats for LSB-First (SAIFB = 1) (continued) BICKI 64 fs 5.2.4 Delay serial clock enable Table 21. Delay serial clock enable Bit 5.2.5 Channel input mapping Table 22. Channel ...
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STA559BWQS 5.3 Configuration register C (addr 0x02 OCRB 1 5.3.1 DDX power output mode Table 23. DXX power output mode Bit The DDX power output mode selects how the DDX output timing is ...
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Register description 5.3.3 Over-current warning detect adjustment bypass Table 27. Over-current warning detect adjustment bypass Bit The OCWARN input is used to indicate an over-current warning condition. When OCWARN is asserted (set to 0), the power control ...
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STA559BWQS 5.4.3 DSP bypass Table 30. DSP bypass Bit Setting the DSPB bit bypasses the EQ functionality of the STA559BWQS. 5.4.4 Post-scale link Table 31. Post-scale link Bit Post-scale functionality can be used for ...
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Register description 5.4.6 Dynamic range compression/anti-clipping bit Table 33. Dynamic range compression/anti-clipping bit Bit Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold ...
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STA559BWQS 5.5 Configuration register E (addr 0x04 SVE ZCE 1 1 5.5.1 Max power correction variable Table 36. Max power correction variable Bit 5.5.2 Max power correction Table 37. Max power correction Bit RW 1 ...
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Register description 5.5.4 AM mode enable Table 39. AM mode enable Bit RW RST 3 RW STA559BWQS features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for ...
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STA559BWQS 5.5.8 Soft volume update enable Table 43. Soft volume update enable Bit RW RST 7 RW 5.6 Configuration register F (addr 0x05 EAPD PWDN 0 5.6.1 Output configuration Table 44. Output configuration Bit ...
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Register description Note: To the left of the arrow is the processing channel. Note that though the defaults are shown, using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs ...
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STA559BWQS 5.6.3 Binary output mode clock loss detection Table 47. Binary output mode clock loss detection Bit Detects loss of input MCLK in binary mode and will output 50% duty cycle. 5.6.4 LRCK double trigger protection Table ...
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Register description 5.6.7 External amplifier power down Table 51. External amplifier power down Bit The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state ...
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STA559BWQS 5.7.4 Channel 2 volume D7 D6 C2V7 C2V6 0 1 5.7.5 Channel 3/line output volume D7 D6 C3V7 C3V6 0 1 The volume structure of the STA559BWQS consists of individual volume registers for each channel and a master volume ...
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Register description Table 54. Channel volume as a function of CxV[7:0] CxV[7:0] 00000010 (0x02) … 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) … 11010111 (0xD7) 11011000 (0xD8) 11011001 (0xD9) 11011010 (0xDA) … 11101100 (0xEC) 11101101 (0xED) … 11111111 (0xFF) 5.8 Auto ...
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STA559BWQS 5.8.3 AM interference frequency switching Table 56. AM interference frequency switching Bit Table 57. AutoMode AM switching frequency selection AMAM[2:0] 000 001 010 011 100 101 110 5.8.4 Bass management crossover Table 58. Bass management crossover ...
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Register description Table 59. Bass management crossover frequency XO[3:0] 1010 1011 1100 1101 1110 1111 5.9 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 5.9.1 Tone ...
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STA559BWQS 5.9.3 Volume bypass Each channel contains an individual channel volume bypass particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the ...
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Register description 5.10 Tone control register (addr 0x11) 5.10.1 Tone control D7 D6 TTC3 TTC2 0 1 Table 62. Tone control boost/cut as a function of BTC and TTC bits 5.11 Dynamics control registers (addr 0x12 - 0x15) 5.11.1 Limiter ...
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STA559BWQS 5.11.4 Limiter 2 attack/release threshold D7 D6 L2AT3 L2AT2 0 1 The STA559BWQS includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping ...
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Register description Table 63. Limiter attack rate as a function of LxA bits. LxA[3:0] Attack rate dB/ms 0000 3.1584 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 ...
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STA559BWQS Dynamic range compression mode Table 67. Limiter attack threshold as a function of LxAT bits (DRC- mode). LxAT[3:0] DRC (dB relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 ...
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Register description 5.12.3 Coefficient b1data register bits 15..8 address D7 D6 C1B15 C1B14 0 5.12.4 Coefficient b1data register bits 7.. C1B7 C1B6 0 5.12.5 Coefficient b2 data register bits 23.. C2B23 C2B22 0 0 5.12.6 Coefficient ...
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STA559BWQS 5.12.10 Coefficient a1 data register bits 7.. C3B7 C3B6 0 5.12.11 Coefficient a2 data register bits 23.. C4B23 C4B22 0 0 5.12.12 Coefficient a2 data register bits 15.. C4B15 C4B14 0 5.12.13 Coefficient ...
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Register description 5.12.17 Coefficient write/read control register D7 D6 Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA559BWQS via RAM. Access to this RAM is available to the user via ...
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STA559BWQS Writing a single coefficient to RAM " write 6-bits of address to I " write top 8-bits of coefficient in I " write middle 8-bits of coefficient in I " write bottom 8-bits of coefficient in I " write ...
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Register description Coefficients stored in the user defined coefficient RAM are referenced in the following manner: CxHy0 = b CxHy1 = b CxHy2 = -a CxHy3 = -a CxHy4 = b where x represents the channel and the y the ...
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STA559BWQS Table 69. RAM block for biquads, mixing, scaling, and bass management Index (Decimal) Index (Hex … … ...
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Register description 5.13 Variable max power correction registers (addr 0x27 - 0x28) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = MPCC15 ...
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STA559BWQS 6 Application 6.1 Application scheme for power supplies Figure 33 below shows a circuit diagram of a typical application for STA559BWQS.Particular care has to be given to the layout of the PCB, especially the power supplies. The 3.3-Ω resistors ...
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Application 6.3 Typical output configuration Figure 35 shows the typical output configuration used for BTL stereo mode. Please refer to the application note for other recommended output configuration schematics. Figure 35. Output configuration for stereo BTL mode OUT1A OUT1A OUT1A ...
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STA559BWQS 7 Package thermal characteristics Due to the high efficiency of the system the dissipated power is negligible, allowing the use of the STA559BWQS without heat sink but using only a small copper area on the PCB. Using a double ...
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Package information 8 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
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STA559BWQS 9 License information Supply of this product does not convey a license under the relevant intellectual property of the companies mentioned in this chapter nor imply any right to use this intellectual property in any finished end-user or ready ...
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Trademarks and other acknowledgements 10 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. QHD and QXpander are registered trademarks of QSound Labs Inc. 64/66 STA559BWQS ...
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STA559BWQS 11 Revision history Table 70. Document revision history Date 28-Mar-2008 Revision 1 Initial release. Revision history Changes 65/66 ...
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...