STA559BWQS13TR STMICROELECTRONICS [STMicroelectronics], STA559BWQS13TR Datasheet - Page 43

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STA559BWQS13TR

Manufacturer Part Number
STA559BWQS13TR
Description
5-V, 2-A, 2.1-channel high-efficiency digital audio system with QSound QHD
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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STA559BWQS
5.7.4
5.7.5
Channel 2 volume
Channel 3/line output volume
The volume structure of the STA559BWQS consists of individual volume registers for each
channel and a master volume register that provides an offset to each channels volume
setting. The individual channel volumes are adjustable in 0.5dB steps from +48 dB to -
80 dB.
As an example if C3V = 00h or +48 dB and MV = 18h or –12 dB, then the total gain for
channel 3 = +36 dB.
The master mute when set to 1 will mute all channels at once, whereas the individual
channel mutes (CxM) will mute only that channel. Both the master mute and the channel
mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from
the maximum volume setting at the internal processing rate (approximately 96 kHz).
A “hard mute” can be obtained by commanding a value of 0xFF (255) to any channel volume
register or the master volume register. When volume offsets are provided via the master
volume register any channel that whose total volume is less than –80 dB will be muted.
All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F)
on a per channel basis as this creates the smoothest possible volume transitions. When
ZCE = 0, volume updates will occur immediately.
Table 53.
Table 54.
C2V7
C3V7
D7
D7
0
0
01001100 (0x4C)
11111110 (0xFE)
11111111 (0xFF)
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
00000000 (0x00)
00000001 (0x01)
CxV[7:0]
MV[7:0]
Master volume offset as a function of MV[7:0]
Channel volume as a function of CxV[7:0]
C2V6
C3V6
D6
D6
1
1
C2V5
C3V5
D5
D5
1
1
C2V4
C3V4
D4
D4
0
0
Volume offset from channel value
C2V3
C3V3
D3
D3
0
0
Hard master mute
-127.5 dB
+47.5 dB
Volume
-0.5 dB
+48 dB
-38 dB
-1 dB
0 dB
C2V2
C3V2
D2
D2
0
0
Register description
C2V1
C3V1
D1
D1
0
0
C2V0
C3V0
D0
D0
0
0
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