PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 71

• Manufacturer Part Number: PEF20525
• Description: 2 Channel Serial Optimized Communication Controller for HDLC/PPP
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 31
To supervise correct function when using bi-phase encoding, a status flag and a
maskable interrupt inform about synchronous/asynchronous state of the DPLL.
3.2.6
Each SCC provides a general purpose timer e.g. to support protocol functions. In all
operating modes the timer is clocked by the effective transmit clock. In clock mode 5
(time-slot oriented mode) the clock source for the timer can be optionally switched to the
frame sync clock (input pin FSC) by setting bit ’SRC’ in register TIMR3.
The timer is controlled by the CPU via access to registers
The timer can be started any time by setting bit ’STI’ in register CMDRL. After the timer
has expired it generates a timer interrupt (’TIN’).
With bit field ’CNT(2..0)’ in register
programmed. If the maximum value ’111’ is entered, a timer interrupt is generated
periodically, with the time period determined by bit field ’TVALUE’ (registers
TIMR0..TIMR3).
The timer can be stopped any time by setting bit ’TRES’ in register
In HDLC Automode the timer is used internally for autonomous protocol functions (refer
to the chapter
register
Data Sheet
DPLL
Count
Correction
Transmit
Clock
Receive
Clock
TIMR3
SCC Timer Operation
“Automode” on Page
DPLL Algorithm for FM0, FM1 and Manchester Encoding
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0
must be set to ’1’.
+PA
Bit Cell (FM Coding)
- ignore -
TIMR3
84). If this operating mode is selected, bit ’TMD’ in
the number of automatic timer restarts can be
71
Bit Cell (Manchester Coding)
-PA
CMDRL
0
0
1
Functional Overview
+PA
2
CMDRL
and TIMR0..TIMR3.
3
4
- ignore -
PEB 20525
PEF 20525
5
to ’1’.
ITD01807
2000-09-14
6
7