PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 175

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PEF20525

Manufacturer Part Number
PEF20525
Description
2 Channel Serial Optimized Communication Controller for HDLC/PPP
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet

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PEB 20525
PEF 20525
Register Description (PCMRX3)
PCMRX
PCM Mask for Receive Direction
This bit field is valid in clock mode 5 only and the PCM mask must be
enabled via bit ’REPCM’ in register RTSA1.
Each bit selects one of 32 (8-bit) receive time-slots. The offset of time-
slot zero to the frame sync pulse can be programmed via register
RTSA1
bit field ’RTSN’.
Data Sheet
5-175
2000-09-14

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